Re: [Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation

2018-02-27 Thread Bastian Koppelmann
On 02/26/2018 11:17 PM, Michael Clark wrote: > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > RISC-V code generator has complete coverage for the Base ISA v2.2, > Privileged ISA v1.9.1 and Privileged ISA v1.10: > > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version

[Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation

2018-02-26 Thread Michael Clark
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II: Privile