Re: [Qemu-devel] [PATCH v8 13/23] RISC-V HART Array

Got it. I can add to the post merge cleanup patch series. BTW the code currently creates a homogeneous array or cores but the intent is that it supports a heterogeneous array, in the future. It might evolve into an SOC base class. We need a method to give it an array or cpu_models. For example the

Re: [Qemu-devel] [PATCH v8 13/23] RISC-V HART Array

On 03/02/2018 02:51 PM, Michael Clark wrote: > Holds the state of a heterogenous array of RISC-V hardware threads. heterogeneous > > Reviewed-by: Richard Henderson > Signed-off-by: Sagar Karandikar > Signed-off-by: Michael Clark

[Qemu-devel] [PATCH v8 13/23] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 89