On Wed, Apr 25, 2018 at 5:08 PM Michael Clark wrote:
> Vectored traps for asynchrounous interrupts are optional.
> The mtvec/stvec mode field is WARL and hence does not trap
> if an illegal value is written. Illegal values are ignored.
> Later we can add RISCV_FEATURE_VECTORED_TRAPS however
> un
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fi
