> > I think some of the previously-implemented similar cases involving
> > read-only bits were handled the same way, and we just built on that. What
> > would you suggest as a more appropriate solution in such cases (of
> > accessing "preset by hardware" bits)?
>
> Well, ctx->insn_flags and
> > I think some of the previously-implemented similar cases involving
> > read-only bits were handled the same way, and we just built on that. What
> > would you suggest as a more appropriate solution in such cases (of
> > accessing "preset by hardware" bits)?
>
> Well, ctx->insn_flags and
On 08/16/2018 10:06 AM, Aleksandar Markovic wrote:
> I think some of the previously-implemented similar cases involving read-only
> bits were handled the same way, and we just built on that. What would you
> suggest as a more appropriate solution in such cases (of accessing "preset by
>
On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> From: Aleksandar Rikalo
>
> Use bits from configuration registers for availability control
> of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
> This is done by adding a field in hflags for MT bit, and adding
> functions
> From: Richard Henderson
> Sent: Thursday, August 16, 2018 6:37 PM
>
> Subject: Re: [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE
> instructions availability control
>
> On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> > From: Aleksandar Rikalo
> >
> > Use bits from configuration
From: Aleksandar Rikalo
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().
Reviewed-by: Aleksandar Markovic
