On Fri, May 03, 2019 at 03:53:07PM +1000, Suraj Jitindar Singh wrote:
> The spr TBU40 is used to set the upper 40 bits of the timebase
> register, present on POWER5+ and later processors.
>
> This register can only be written by the hypervisor, and cannot be read.
>
> Signed-off-by: Suraj
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh
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hw/ppc/ppc.c| 13 +
