On 2019/8/29 下午10:06, Chih-Min Chao wrote:
Hi Liuzhiwei,
Some comments:
1. vector extension allows flexible implementation. It is better
to describe the limitation of current implementation (such as
vlen/elen/slen) , supported sections and unsupported features.
Thanks! All mentioned will be in patch V2.
2. there should be cfg.ext_v to turn on vector extension from
command line
I will add the vector extension to cpu "any". Is it all right?
3. from license
It should be "Copyright (c) 2019 C-SKY Limited, All
rights reserved." but not "2011 ~ 2019"
It is huge work wait and thanks for your contribution.
chihmin
On Wed, Aug 28, 2019 at 3:06 PM liuzhiwei <zhiwei_...@c-sky.com
<mailto:zhiwei_...@c-sky.com>> wrote:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei <zhiwei_...@c-sky.com
<mailto:zhiwei_...@c-sky.com>>
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
linux-user/riscv/cpu_loop.c | 8 +-
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 30 +
target/riscv/cpu_bits.h | 15 +
target/riscv/cpu_helper.c | 7 +
target/riscv/csr.c | 65 +-
target/riscv/helper.h | 354 +
target/riscv/insn32.decode | 374 +-
target/riscv/insn_trans/trans_rvv.inc.c | 484 +
target/riscv/translate.c | 1 +
target/riscv/vector_helper.c | 26563
++++++++++++++++++++++++++++++
13 files changed, 28017 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
