Re: [Qemu-devel] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

2017-01-31 Thread David Gibson
On Fri, Jan 13, 2017 at 05:28:12PM +1100, Suraj Jitindar Singh wrote: > The vpm0 bit was removed from the LPCR in POWER9, this bit controlled > whether ISI and DSI interrupts were directed to the hypervisor or the > partition. These interrupts now go to the hypervisor irrespective, thus > it is no

[Qemu-devel] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

2017-01-12 Thread Suraj Jitindar Singh
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled whether ISI and DSI interrupts were directed to the hypervisor or the partition. These interrupts now go to the hypervisor irrespective, thus it is no longer necessary to check the vmp0 bit in the LPCR. Signed-off-by: Suraj