On Mon, Dec 10, 2018 at 10:52:18AM -0200, Fabiano Rosas wrote:
> David Gibson writes:
>
> >> >> +if (arch_info->address == trace_handler_addr) {
> >> >> +cpu_synchronize_state(cs);
> >> >> +kvm_remove_breakpoint(cs, trace_handler_addr, 4,
> >> >> GDB_BREAKPOINT_SW);
> >> >> +
David Gibson writes:
>> >> +if (arch_info->address == trace_handler_addr) {
>> >> +cpu_synchronize_state(cs);
>> >> +kvm_remove_breakpoint(cs, trace_handler_addr, 4,
>> >> GDB_BREAKPOINT_SW);
>> >> +
>> >> +cpu_memory_rw_debug(cs, env->spr[SPR_SRR0] - 4, (uint8_t *)&i
On Fri, Nov 30, 2018 at 06:46:21PM -0200, Fabiano Rosas wrote:
> David Gibson writes:
>
> >> --- a/target/ppc/kvm.c
> >> +++ b/target/ppc/kvm.c
> >> @@ -94,6 +94,7 @@ static int cap_ppc_safe_indirect_branch;
> >> static int cap_ppc_nested_kvm_hv;
> >>
> >> static uint32_t debug_inst_opcode;
>
David Gibson writes:
>> --- a/target/ppc/kvm.c
>> +++ b/target/ppc/kvm.c
>> @@ -94,6 +94,7 @@ static int cap_ppc_safe_indirect_branch;
>> static int cap_ppc_nested_kvm_hv;
>>
>> static uint32_t debug_inst_opcode;
>> +static target_ulong trace_handler_addr;
>>
>> /* XXX We have a race condi
On Wed, Nov 21, 2018 at 04:13:47PM -0200, Fabiano Rosas wrote:
> The hardware singlestep mechanism in POWER works via a Trace Interrupt
> (0xd00) that happens after any instruction executes, whenever MSR_SE =
> 1 (PowerISA Section 6.5.15 - Trace Interrupt).
>
> However, with kvm_hv, the Trace Inte
The hardware singlestep mechanism in POWER works via a Trace Interrupt
(0xd00) that happens after any instruction executes, whenever MSR_SE =
1 (PowerISA Section 6.5.15 - Trace Interrupt).
However, with kvm_hv, the Trace Interrupt happens inside the guest and
KVM has no visibility of it. Therefore
