On Mon, Jun 16, 2014 at 05:46:24PM +1000, Peter Crosthwaite wrote:
On Mon, Jun 16, 2014 at 5:40 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 10 June 2014 02:32, Alistair Francis alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore.
I think
Il 17/06/2014 09:16, Stefan Hajnoczi ha scritto:
The bigger issue though is how do you do an N:1 mapping. The container
should only have 1 midr prop, but it should mirror to all contained
CPUs. Should we add multiplicity to the aliasing feature?
If we'll need 1:N alias properties in other
On Tue, Jun 17, 2014 at 6:05 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 17/06/2014 09:16, Stefan Hajnoczi ha scritto:
The bigger issue though is how do you do an N:1 mapping. The container
should only have 1 midr prop, but it should mirror to all contained
CPUs. Should we add
On Tue, Jun 17, 2014 at 8:12 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Tue, Jun 17, 2014 at 6:05 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 17/06/2014 09:16, Stefan Hajnoczi ha scritto:
The bigger issue though is how do you do an N:1 mapping. The container
should
On Mon, Jun 16, 2014 at 2:43 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make sure no other CPUs exist and if
On 10 June 2014 02:32, Alistair Francis alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore.
I think this is in general the right way to go.
+/* Properties for the A9 CPU */
+DEFINE_PROP_UINT32(midr, A9MPPrivState, midr, 0),
+
On Mon, Jun 16, 2014 at 5:40 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 10 June 2014 02:32, Alistair Francis alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore.
I think this is in general the right way to go.
+/* Properties for the A9 CPU
Am 16.06.2014 06:43, schrieb Peter Crosthwaite:
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make sure no other CPUs exist and if
they do the Cortex-A9 won't be added. This
Am 16.06.2014 08:04, schrieb Alistair Francis:
On Mon, Jun 16, 2014 at 2:43 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a
On Mon, Jun 16, 2014 at 8:19 PM, Andreas Färber afaer...@suse.de wrote:
Am 16.06.2014 06:43, schrieb Peter Crosthwaite:
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make
On 16 June 2014 11:19, Andreas Färber afaer...@suse.de wrote:
Am 16.06.2014 06:43, schrieb Peter Crosthwaite:
So you could add an integer property listener to init them earlier (or
even do dynamic extending/freeing or the allocated CPUs). I'm not sure
exactly what we are really supposed to do
Am 16.06.2014 12:34, schrieb Peter Crosthwaite:
On Mon, Jun 16, 2014 at 8:19 PM, Andreas Färber afaer...@suse.de wrote:
However a more fundamental issue that PMM was unsure about is whether
the CPUs should be child of MPCore as done here or a sibling of the
MPCore container.
I'll go with
On 16 June 2014 11:58, Andreas Färber afaer...@suse.de wrote:
Well, for Cortex-A9 that may work. But Cortex-A15 (and Cortex-A5x if
existant by now) should also be refactored alongside, as proof of
concept - can you really create num_cpu cortex-a15 CPUs on the MPCore
for a big.LITTLE
Am 16.06.2014 13:11, schrieb Peter Maydell:
On 16 June 2014 11:58, Andreas Färber afaer...@suse.de wrote:
Well, for Cortex-A9 that may work. But Cortex-A15 (and Cortex-A5x if
existant by now) should also be refactored alongside, as proof of
concept - can you really create num_cpu cortex-a15
Am 16.06.2014 12:44, schrieb Peter Maydell:
On 16 June 2014 11:19, Andreas Färber afaer...@suse.de wrote:
Am 16.06.2014 06:43, schrieb Peter Crosthwaite:
So you could add an integer property listener to init them earlier (or
even do dynamic extending/freeing or the allocated CPUs). I'm not
On 16 June 2014 12:18, Andreas Färber afaer...@suse.de wrote:
Am 16.06.2014 12:44, schrieb Peter Maydell:
I think property-listeners was the mechanism we talked
about for when you need to do something before realize
but it depends on some property, yes.
Got a pointer to that? Waiting for
On Mon, Jun 16, 2014 at 9:11 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 16 June 2014 11:58, Andreas Färber afaer...@suse.de wrote:
Well, for Cortex-A9 that may work. But Cortex-A15 (and Cortex-A5x if
existant by now) should also be refactored alongside, as proof of
concept - can you
Am 16.06.2014 13:22, schrieb Peter Crosthwaite:
On Mon, Jun 16, 2014 at 9:11 PM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 16 June 2014 11:58, Andreas Färber afaer...@suse.de wrote:
Besides, not all CPUs have an MPCore, Cortex-A8 and Cortex-A5 come to
mind, so we should be aware that
Ping
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make sure no other CPUs exist and if
they do the Cortex-A9 won't be added. This is implemented to
maintain compatibility
On Tue, Jun 10, 2014 at 11:32 AM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make sure no other CPUs exist and if
they do the Cortex-A9 won't be added. This is implemented to
maintain compatibility and can
This patch adds the Cortex-A9 ARM CPU to the A9MPCore. It
first does a check to make sure no other CPUs exist and if
they do the Cortex-A9 won't be added. This is implemented to
maintain compatibility and can be removed once all machines
have been updated
This patch also allows the midr and
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