Thanks for the comments Fabiano.
On 05/22/2019 11:38 PM, Fabiano Rosas wrote:
Shivaprasad G Bhat writes:
+
+ddc = NVDIMM_GET_CLASS(nvdimm);
+ddc->read_label_data(nvdimm, [0], numBytesToRead, offset);
+
+return H_SUCCESS;
+}
+
+
+static target_ulong
On 05/14/2019 10:08 AM, David Gibson wrote:
On Mon, May 13, 2019 at 04:28:36AM -0500, Shivaprasad G Bhat wrote:
This patch implements few of the necessary hcalls for the nvdimm support.
PAPR semantics is such that each NVDIMM device is comprising of multiple
SCM(Storage Class Memory)
On Wed, May 22, 2019 at 03:08:34PM -0300, Fabiano Rosas wrote:
> Shivaprasad G Bhat writes:
>
> > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> > index 6c16d2b120..b6e7d04dcf 100644
> > --- a/hw/ppc/spapr_hcall.c
> > +++ b/hw/ppc/spapr_hcall.c
> > @@ -3,11 +3,13 @@
> > #include
Fabiano Rosas writes:
>> +nvdimm = NVDIMM(drc->dev);
>> +if ((offset + numBytesToRead < offset) ||
>> +(nvdimm->label_size < numBytesToRead + offset)) {
>> +return H_P2;
>> +}
>
> Won't the first clause always be false? Considering they're both uint64_t.
Neverming
Shivaprasad G Bhat writes:
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 6c16d2b120..b6e7d04dcf 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -3,11 +3,13 @@
> #include "sysemu/hw_accel.h"
> #include "sysemu/sysemu.h"
> #include "qemu/log.h"
>
On Mon, May 13, 2019 at 04:28:36AM -0500, Shivaprasad G Bhat wrote:
> This patch implements few of the necessary hcalls for the nvdimm support.
>
> PAPR semantics is such that each NVDIMM device is comprising of multiple
> SCM(Storage Class Memory) blocks. The guest requests the hypervisor to
This patch implements few of the necessary hcalls for the nvdimm support.
PAPR semantics is such that each NVDIMM device is comprising of multiple
SCM(Storage Class Memory) blocks. The guest requests the hypervisor to bind
each of the SCM blocks of the NVDIMM device using hcalls. There can be
SCM
