Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-22 Thread Sergey Fedorov
On 21/06/16 17:52, Pranith Kumar wrote: > Hi Sergey, > > On Mon, Jun 20, 2016 at 5:21 PM, Sergey Fedorov wrote: >> On 18/06/16 07:03, Pranith Kumar wrote: >>> diff --git a/tcg/tcg.h b/tcg/tcg.h >>> index db6a062..36feca9 100644 >>> --- a/tcg/tcg.h >>> +++ b/tcg/tcg.h >>> @@

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Richard Henderson
On 06/21/2016 11:23 AM, Alex Bennée wrote: If you think I should rebase on mainine, I will do so with the changes you suggested above. Well I'll be guided by what Richard thinks about the chances of this merging ahead of the main MTTCG patches. You were mentioning the trouble with testing with

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Alex Bennée
Pranith Kumar writes: > On Tue, Jun 21, 2016 at 2:04 PM, Alex Bennée wrote: >> >> Pranith Kumar writes: >> >>> This commit introduces the TCGOpcode for memory barrier instruction. >>> >>> This opcode takes an argument which

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Pranith Kumar
On Tue, Jun 21, 2016 at 2:04 PM, Alex Bennée wrote: > > Pranith Kumar writes: > >> This commit introduces the TCGOpcode for memory barrier instruction. >> >> This opcode takes an argument which is the type of memory barrier >> which should be

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Pranith Kumar
On Tue, Jun 21, 2016 at 11:09 AM, Alex Bennée wrote: >>> +TCG_BAR_SC = 128, >>> >>> How's that different from TCG_MO_ALL? >> >> TCG_BAR_* tells us what ordering is enforced. TCG_MO_* tells what on >> what operations the ordering is to be enforced. > > This

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Alex Bennée
Pranith Kumar writes: > This commit introduces the TCGOpcode for memory barrier instruction. > > This opcode takes an argument which is the type of memory barrier > which should be generated. > > Signed-off-by: Pranith Kumar > Signed-off-by:

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Alex Bennée
Pranith Kumar writes: > Hi Sergey, > > On Mon, Jun 20, 2016 at 5:21 PM, Sergey Fedorov wrote: >> On 18/06/16 07:03, Pranith Kumar wrote: >>> diff --git a/tcg/tcg.h b/tcg/tcg.h >>> index db6a062..36feca9 100644 >>> --- a/tcg/tcg.h >>> +++ b/tcg/tcg.h

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Pranith Kumar
Hi Sergey, On Mon, Jun 20, 2016 at 5:21 PM, Sergey Fedorov wrote: > On 18/06/16 07:03, Pranith Kumar wrote: >> diff --git a/tcg/tcg.h b/tcg/tcg.h >> index db6a062..36feca9 100644 >> --- a/tcg/tcg.h >> +++ b/tcg/tcg.h >> @@ -408,6 +408,20 @@ static inline intptr_t

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-21 Thread Paolo Bonzini
On 18/06/2016 06:03, Pranith Kumar wrote: > +typedef enum { > +TCG_MO_LD_LD= 1, > +TCG_MO_ST_LD= 2, > +TCG_MO_LD_ST= 4, > +TCG_MO_ST_ST= 8, I like the idea of making this a bitmask. However, most of the code you wrote for the backends looks at these as an enum.

Re: [Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-20 Thread Sergey Fedorov
On 18/06/16 07:03, Pranith Kumar wrote: > diff --git a/tcg/tcg.h b/tcg/tcg.h > index db6a062..36feca9 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -408,6 +408,20 @@ static inline intptr_t QEMU_ARTIFICIAL > GET_TCGV_PTR(TCGv_ptr t) > #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1) > #define

[Qemu-devel] [RFC v3 PATCH 01/14] Introduce TCGOpcode for memory barrier

2016-06-17 Thread Pranith Kumar
This commit introduces the TCGOpcode for memory barrier instruction. This opcode takes an argument which is the type of memory barrier which should be generated. Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/README| 17