Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

2016-06-22 Thread Alex Bennée
Richard Henderson writes: > On 06/22/2016 09:25 AM, Alex Bennée wrote: >> >> Pranith Kumar writes: >> >>> Generate mfence/sfence/lfence instruction on SSE2 enabled >>> processors. For older processors, generate a 'lock orl $0,0(%esp)' >>> instruction

Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

2016-06-22 Thread Richard Henderson
On 06/22/2016 09:25 AM, Alex Bennée wrote: > > Pranith Kumar writes: > >> Generate mfence/sfence/lfence instruction on SSE2 enabled >> processors. For older processors, generate a 'lock orl $0,0(%esp)' >> instruction which has full ordering semantics. >> >> Signed-off-by:

Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

2016-06-22 Thread Alex Bennée
Pranith Kumar writes: > Generate mfence/sfence/lfence instruction on SSE2 enabled > processors. For older processors, generate a 'lock orl $0,0(%esp)' > instruction which has full ordering semantics. > > Signed-off-by: Pranith Kumar > [rth: Check

Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

2016-06-21 Thread Paolo Bonzini
On 18/06/2016 06:03, Pranith Kumar wrote: > Generate mfence/sfence/lfence instruction on SSE2 enabled > processors. For older processors, generate a 'lock orl $0,0(%esp)' > instruction which has full ordering semantics. > > Signed-off-by: Pranith Kumar > [rth: Check for

[Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

2016-06-17 Thread Pranith Kumar
Generate mfence/sfence/lfence instruction on SSE2 enabled processors. For older processors, generate a 'lock orl $0,0(%esp)' instruction which has full ordering semantics. Signed-off-by: Pranith Kumar [rth: Check for sse2, fallback to locked memory op otherwise.]