On 10/01/2015 03:32 PM, Pranith Kumar wrote:
> On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington
> wrote:
>>
>> Are you using KVM or TCG (are you running on an x86 host or an arm64 host)?
>
> I am using TCG, aarch64-softmmu on x86 host.
>
>>
>> We have published some patches implementing th
On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington
wrote:
>
> Are you using KVM or TCG (are you running on an x86 host or an arm64 host)?
I am using TCG, aarch64-softmmu on x86 host.
>
> We have published some patches implementing the PMU registers and instruction
> counting (but not any oth
Hi Pranith,
On 10/01/2015 11:34 AM, Pranith Kumar wrote:
> Hi Christoph,
>
> On the qemu mailing list you mentioned that you use perf events in
> linux ARM64 guests. I was wondering how you enabled access to the PMU?
>
> I get illegal instruction whenever I execute any "MSR PMUSERENR_EL0,
> 1"
