On Fri, May 28, 2010 at 9:53 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
32m: 0x12fff394
64m: 0x14fff394
192m:0x1cfff394
256m:0x20fff394
Memory probing? It would be strange that OS would do it itself. The OS
could just
ask OBP how much does it have. Here is the listing where it
32m: 0x12fff394
64m: 0x14fff394
192m:0x1cfff394
256m:0x20fff394
Memory probing? It would be strange that OS would do it itself. The OS
could just
ask OBP how much does it have. Here is the listing where it happens:
_swift_vac_rgnflush: rd %psr, %g2
_swift_vac_rgnflush+4:
Artyom Tarasenko wrote:
Was going to put some more empty slots into SS-10/20 (VSIMMs, SX)
after we are done with SS-5 (due to technical limitations I can switch
access from one real SS model to another one once a few days only).
I have a partial implementation of the SS-20 VSIMM (cg14) that
2010/5/25 Blue Swirl blauwir...@gmail.com:
On Tue, May 25, 2010 at 5:00 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/21 Blue Swirl blauwir...@gmail.com:
On Fri, May 21, 2010 at 5:23 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
2010/5/21 Blue Swirl blauwir...@gmail.com:
On Fri, May 21, 2010 at 5:23 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom
On Tue, May 25, 2010 at 5:00 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/21 Blue Swirl blauwir...@gmail.com:
On Fri, May 21, 2010 at 5:23 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/9/10, Artyom Tarasenko
On Fri, May 21, 2010 at 5:23 PM, Artyom Tarasenko
atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/9/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/8/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On the real
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/9/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/8/10, Artyom Tarasenko
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/10 Blue Swirl blauwir...@gmail.com:
On 5/10/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/9/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue
On 5/8/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software shouldn't use aliased addresses, neither should it crash
when it uses (on the real hardware it wouldn't). Using empty_slot
instead of aliasing can help
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/8/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software shouldn't use aliased addresses, neither should it crash
when it uses (on the real hardware it wouldn't). Using
On 5/9/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/8/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software shouldn't use aliased addresses, neither should
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/9/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
2010/5/9 Blue Swirl blauwir...@gmail.com:
On 5/8/10, Artyom Tarasenko atar4q...@googlemail.com wrote:
On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software
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