On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
On uncorrectable error status register in pcie_aer_write_config().
The register is RW1CS, so making it writable and test-and-clear doesn't
work.
Sure. But isn't this what w1cmask implements?
Also - mail to ad...@khaleel.us seems
On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
Here is v5 of the pcie patch series.
I hope I addressed the blockers.
On uncorrectable error status register in pcie_aer_write_config().
The register is RW1CS, so making it writable and test-and-clear doesn't
work.
new
On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
Here is v5 of the pcie patch series.
I hope I addressed the blockers.
On uncorrectable error status register in pcie_aer_write_config().
The register is RW1CS, so making it writable and test-and-clear doesn't
work.
new
Isaku Yamahata (14):
pci: introduce helper functions to test-and-{clear, set} mask in
configuration space
pci: introduce helper function to handle msi-x and msi.
pci: use pci_word_test_and_clear_mask() in pci_device_reset()
pci/bridge: fix pci_bridge_reset()
msi:
On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
On uncorrectable error status register in pcie_aer_write_config().
The register is RW1CS, so making it writable and test-and-clear doesn't
work.
Sure. But
Are all these patches going to be integrated into the current qemu repository?
-AK
_
From: Isaku Yamahata [mailto:yamah...@valinux.co.jp]
To: Michael S. Tsirkin [mailto:m...@redhat.com]
Cc: qemu-devel@nongnu.org, skand...@cisco.com, etmar...@cisco.com,
we...@cisco.com, ad...@khaleel.us
On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
On uncorrectable error status register in pcie_aer_write_config().
The register is RW1CS, so
On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
On uncorrectable error
On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan Khaleel wrote:
Are all these patches going to be integrated into the current qemu repository?
Eventually. Right now some of them are merged into Michael's pci branch.
It's up to Michael when he requests Anthony to pull the branch.
thanks,
-AK
On Wed, Oct 20, 2010 at 07:36:37AM +0900, Isaku Yamahata wrote:
On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
On Tue, Oct 19, 2010 at
On Wed, Oct 20, 2010 at 12:40:49AM +0200, Michael S. Tsirkin wrote:
I think I suggested once a good way to implement this:
- always make the bits w1c
- after config write:
if MHR is enabled, and you see that error log is not empty and that bit is
0,
this means that someone has
Isaku,
Good work! One question here: any plan to put q35 and seabios into mainline?
FYI: I have made pcie plus q35 working on qemu-kvm, though on a little bit
old code base.
Wei
On 10/19/10 3:39 PM, Isaku Yamahata yamah...@valinux.co.jp wrote:
On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan
On Wed, Oct 20, 2010 at 07:55:56AM +0900, Isaku Yamahata wrote:
On Wed, Oct 20, 2010 at 12:40:49AM +0200, Michael S. Tsirkin wrote:
I think I suggested once a good way to implement this:
- always make the bits w1c
- after config write:
if MHR is enabled, and you see that error log
On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
Good work! One question here: any plan to put q35 and seabios into mainline?
My plan is
qemu part:
1. respin this patch. Mainly aer part. I'm here
2. address bus reset and flr.
3. Then move on to q35 north/south bridge.
After 1 or 2, it
Isaku,
Sure I will send out patch after some cleanup. MSI using irq-in-kernel still
a little bit ugly:)
Wei
On 10/19/10 4:17 PM, Isaku Yamahata yamah...@valinux.co.jp wrote:
On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
Good work! One question here: any plan to put q35 and seabios
On Wed, Oct 20, 2010 at 08:17:24AM +0900, Isaku Yamahata wrote:
On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
Good work! One question here: any plan to put q35 and seabios into mainline?
My plan is
qemu part:
1. respin this patch. Mainly aer part. I'm here
2. address bus reset
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