On 11/18/20 12:29 AM, frank.ch...@sifive.com wrote:
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw 0110 . 001 . 0011011 @r2
> +ctzw 0111 . 001 . 0011011 @r2
Oh, one more thing. In the draft, the top decode bits are split into two
On 11/18/20 12:29 AM, frank.ch...@sifive.com wrote:
> +static bool gen_cxzw(DisasContext *ctx, arg_r2 *a,
> + void(*func)(TCGv_i32, TCGv_i32, uint32_t))
...
> +static bool gen_cxz(DisasContext *ctx, arg_r2 *a,
> +void(*func)(TCGv, TCGv, target_ulong))
I
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47
target/riscv/translate.c| 48
