On 11/12/21 3:14 AM, yangxiaojuan wrote:
+#define EXCODE_IP 64
What's this?
The manual 6.1.3 says the exception number of an interrupt is the exception
number plus an offset of 64. This defines the offset, sorry, the name is bad,
maybe change a name or just use 64 dire
Hi, Richard,
On 11/11/2021 09:29 PM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> +#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
>> +
>
> Missing bitfield definitions for misc.
>
At present, there is no read/write to each field of misc register so it is
On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
@@ -179,12 +181,22 @@ static void loongarch_cpu_reset(DeviceState *dev)
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env;
+uint64_t data;
lacc-
On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
+#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
+
Missing bitfield definitions for misc.
+#define EXCODE_IP 64
What's this?
+#define EXCCODE_INT 0
+#define EXCCODE_PIL 1
+#define EX
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 334 +
target/loongarch/cpu.c | 12 ++
target/loongarch/cpu.h | 127 ++
3 f
