From: Frank Chang <frank.ch...@sifive.com> Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 9 +++++++ target/riscv/csr.c | 59 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d2bb7e7003..674ee4dc999 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -180,6 +180,10 @@ struct CPURISCVState { target_ulong mtval; /* since: priv-1.10.0 */ /* NMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; bool nmie; target_ulong nmip; target_ulong rnmi_irqvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8e5f0be599a..a376ede0cc5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -166,6 +166,12 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +/* NMI */ +#define CSR_MNSCRATCH 0x350 +#define CSR_MNEPC 0x351 +#define CSR_MNCAUSE 0x352 +#define CSR_MNSTATUS 0x353 + /* Legacy Machine Trap Handling (priv v1.9.1) */ #define CSR_MBADADDR 0x343 @@ -558,6 +564,9 @@ #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_MPP MSTATUS_MPP + /* Interrupt causes */ #define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bfb..489d6d90e68 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -188,6 +188,11 @@ static int pmp(CPURISCVState *env, int csrno) { return -!riscv_feature(env, RISCV_FEATURE_PMP); } + +static int nmi(CPURISCVState *env, int csrno) +{ + return -!riscv_feature(env, RISCV_FEATURE_RNMI); +} #endif /* User Floating-Point CSRs */ @@ -713,6 +718,54 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) return 0; } +static int read_mnscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnscratch; + return 0; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch = val; + return 0; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnepc; + return 0; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc = val; + return 0; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mncause; + return 0; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause = val; + return 0; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnstatus; + return 0; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnstatus = val & MNSTATUS_MPP; + return 0; +} + static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { @@ -1428,6 +1481,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, + /* NMI */ + [CSR_MNSCRATCH] = { "mnscratch", nmi, read_mnscratch, write_mnscratch }, + [CSR_MNEPC] = { "mnepc", nmi, read_mnepc, write_mnepc }, + [CSR_MNCAUSE] = { "mncause", nmi, read_mncause, write_mncause }, + [CSR_MNSTATUS] = { "mnstatus", nmi, read_mnstatus, write_mnstatus }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus }, [CSR_SIE] = { "sie", smode, read_sie, write_sie }, -- 2.17.1