Re: [v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

On Thu, Jan 4, 2024 at 6:46 PM Alistair Francis wrote: > > On Fri, Dec 29, 2023 at 12:08 PM Atish Patra wrote: > > > > From: Kaiwen Xue > > > > This adds the definitions for ISA extension smcntrpmf. > > > > Signed-off-by: Kaiwen Xue > > Signed-off-by: Atish Patra > > --- > >

Re: [v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

On Fri, Dec 29, 2023 at 12:08 PM Atish Patra wrote: > > From: Kaiwen Xue > > This adds the definitions for ISA extension smcntrpmf. > > Signed-off-by: Kaiwen Xue > Signed-off-by: Atish Patra > --- > target/riscv/cpu.c | 1 - > target/riscv/cpu.h | 6 ++ >

[v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 - target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 3 files changed, 35 insertions(+),

[v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 - target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 3 files changed, 35 insertions(+),