Hello Nick,
It helped a lot.
The page table is software loaded on the MMU of the target I'm using.
I'll watch for TLBs as recommended.
Thank you,
Junho
2024년 1월 23일 (화) 오후 4:36, Nicholas Piggin 님이 작성:
> On Mon Jan 22, 2024 at 6:54 PM AEST, Thomas Huth wrote:
> > On 22/01/2024 05.11, Junho
On Mon Jan 22, 2024 at 6:54 PM AEST, Thomas Huth wrote:
> On 22/01/2024 05.11, Junho wrote:
> > Hello,
> >
> > I'm a QEMU user with PowerPc target architecture.
> > I have some personal modifications related to tb jmp cache and chaining
> > logic to improve the performance of a specific guest
On 22/01/2024 05.11, Junho wrote:
Hello,
I'm a QEMU user with PowerPc target architecture.
I have some personal modifications related to tb jmp cache and chaining
logic to improve the performance of a specific guest code. To verify the
safety, I have to guarantee that the page table on RAM
Hello,
I'm a QEMU user with PowerPc target architecture.
I have some personal modifications related to tb jmp cache and chaining
logic to improve the performance of a specific guest code. To verify the
safety, I have to guarantee that the page table on RAM does not change
after initialization. Do
