On Fri, 25 Dec 2020 at 23:45, BALATON Zoltan via wrote:
> For the Bamboo board we have 4 interrupts connected to the PCI bus in the
> board but also have a comment in ppc4xx_pci.c near the above function
> saying:
>
> /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
>
On Mon, 28 Dec 2020, Mark Cave-Ayland wrote:
On 24/12/2020 08:11, BALATON Zoltan via wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
[ ... ]
If we need legacy mode then we may be able to emulate that by setting
BARs
to
On 24/12/2020 08:11, BALATON Zoltan via wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
[ ... ]
If we need legacy mode then we may be able to emulate that by setting BARs
to legacy ports ignoring what values are written to them
On Tue, 22 Dec 2020, Guenter Roeck wrote:
On 12/22/20 10:23 AM, Mark Cave-Ayland wrote:
On 22/12/2020 16:16, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to
On Thu, 24 Dec 2020, Philippe Mathieu-Daudé wrote:
On Thu, Dec 24, 2020 at 9:11 AM BALATON Zoltan wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
[ ... ]
If we need legacy mode then we may be able to emulate that by setting
On Thu, Dec 24, 2020 at 9:11 AM BALATON Zoltan wrote:
> On Wed, 23 Dec 2020, Guenter Roeck wrote:
> > On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
> > [ ... ]
> >>
> >> If we need legacy mode then we may be able to emulate that by setting BARs
> >> to legacy ports ignoring what
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
[ ... ]
If we need legacy mode then we may be able to emulate that by setting BARs
to legacy ports ignoring what values are written to them if legacy mode
config is set (which may be what
On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote:
[ ... ]
>
> If we need legacy mode then we may be able to emulate that by setting BARs
> to legacy ports ignoring what values are written to them if legacy mode
> config is set (which may be what the real chip does) and we already
在 2020/12/24 上午9:34, BALATON Zoltan 写道:
On Thu, 24 Dec 2020, BALATON Zoltan wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
v3.1:
pci :00:05.1: [Firmware Bug]: reg 0x10: invalid BAR (can't size)
pci :00:05.1: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci :00:05.1:
On Thu, 24 Dec 2020, BALATON Zoltan wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
v3.1:
pci :00:05.1: [Firmware Bug]: reg 0x10: invalid BAR (can't size)
pci :00:05.1: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
pci :00:05.1: [Firmware Bug]: reg 0x18: invalid BAR (can't
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On 12/23/20 12:20 PM, BALATON Zoltan wrote:
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On 12/23/20 8:09 AM, Mark Cave-Ayland wrote:
On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
FWIW bisecting Fuloong2E starts failing here:
On Wed, Dec 23, 2020 at 11:47 PM Guenter Roeck wrote:
>
> On Wed, Dec 23, 2020 at 10:05:12PM +, Mark Cave-Ayland wrote:
> > On 23/12/2020 21:01, Guenter Roeck wrote:
> >
> > > I don't have a real machine, and therefore did not test it on one.
> > >
> > > I tried with Linux mainline
On Wed, Dec 23, 2020 at 10:05:12PM +, Mark Cave-Ayland wrote:
> On 23/12/2020 21:01, Guenter Roeck wrote:
>
> > I don't have a real machine, and therefore did not test it on one.
> >
> > I tried with Linux mainline (v5.10-12913-g614cb5894306), v3.16.85, v4.4.248,
> > and v4.14.212. I can't
On 23/12/2020 21:01, Guenter Roeck wrote:
I don't have a real machine, and therefore did not test it on one.
I tried with Linux mainline (v5.10-12913-g614cb5894306), v3.16.85, v4.4.248,
and v4.14.212. I can't test older version because my cross compiler is too
new. Each of those kernel
On 12/23/20 12:20 PM, BALATON Zoltan wrote:
> On Wed, 23 Dec 2020, Guenter Roeck wrote:
>> On 12/23/20 8:09 AM, Mark Cave-Ayland wrote:
>>> On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
>>>
On 12/22/20 5:16 PM, Guenter Roeck wrote:
> Hi,
>
> commit 459ca8bfa41 ("pci: Assert
On Wed, 23 Dec 2020, Guenter Roeck wrote:
On 12/23/20 8:09 AM, Mark Cave-Ayland wrote:
On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
On 12/22/20 5:16 PM, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added
On Wed, 23 Dec 2020, Philippe Mathieu-Daudé wrote:
On 12/22/20 5:16 PM, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes sense,
On 23/12/2020 13:17, BALATON Zoltan via wrote:
On Wed, 23 Dec 2020, Mark Cave-Ayland wrote:
On 22/12/2020 21:23, Guenter Roeck wrote:
(Added jiaxun.y...@flygoat.com as CC)
Are you sure? It does not show up on cc list for me so unless the list ate it you
might have forgotten to copy the
On 23/12/2020 17:01, Guenter Roeck wrote:
On 12/23/20 8:09 AM, Mark Cave-Ayland wrote:
On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
On 12/22/20 5:16 PM, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added
On 12/23/20 8:09 AM, Mark Cave-Ayland wrote:
> On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
>
>> On 12/22/20 5:16 PM, Guenter Roeck wrote:
>>> Hi,
>>>
>>> commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
>>> pci_bus_change_irq_level") added sanity checks to the
On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote:
On 12/22/20 5:16 PM, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes
On 12/22/20 5:16 PM, Guenter Roeck wrote:
> Hi,
>
> commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
> pci_bus_change_irq_level") added sanity checks to the interrupt number passed
> to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count
> is indexed and
On Wed, 23 Dec 2020, Mark Cave-Ayland wrote:
On 22/12/2020 22:23, BALATON Zoltan via wrote:
I've just remembered that for sam460ex we had this commit: 484ab3dffadc
(sam460ex: Fix PCI interrupts with multiple devices) that changed that
mapping for that machine so I guess you got the exception
On Tue, 22 Dec 2020, Guenter Roeck wrote:
On 12/22/20 2:57 PM, BALATON Zoltan wrote:
[ ... ]
I've already forgot about the details but we have analysed it quite throughly
back when the via ide changes were made. Here are some random pointers to
threads that could have some info:
This was
On Wed, 23 Dec 2020, Mark Cave-Ayland wrote:
On 22/12/2020 21:23, Guenter Roeck wrote:
(Added jiaxun.y...@flygoat.com as CC)
Are you sure? It does not show up on cc list for me so unless the list ate
it you might have forgotten to copy the address there. Done now just in
case, sorry if this
On 22/12/2020 22:23, BALATON Zoltan via wrote:
I've just remembered that for sam460ex we had this commit: 484ab3dffadc (sam460ex:
Fix PCI interrupts with multiple devices) that changed that mapping for that machine
so I guess you got the exception with the bamboo board then. I'm not sure
On 22/12/2020 21:23, Guenter Roeck wrote:
(Added jiaxun.y...@flygoat.com as CC)
I don't really have a good solution for pci_bonito_map_irq(). It may not
matter much - I have not been able to boot fuloong_2e since qemu v4.0,
and afaics that is the only platform using it. Maybe it is just
On 22/12/2020 21:23, Guenter Roeck wrote:
ppc4xx_pci_map_irq() is definitely buggy. I just don't know what the
correct mapping should be. slot & 3, maybe ?
Yeah that doesn't look right. Certainly both the Mac PPC machines use ((pci_dev->devfn
>> 3)) & 3) plus the interrupt pin so I think
On 12/22/20 2:57 PM, BALATON Zoltan wrote:
[ ... ]
> I've already forgot about the details but we have analysed it quite throughly
> back when the via ide changes were made. Here are some random pointers to
> threads that could have some info:
> This was the final solution that was merged as
On 12/22/20 2:23 PM, BALATON Zoltan wrote:
> On Tue, 22 Dec 2020, BALATON Zoltan via wrote:
>> Hello,
>>
>> On Tue, 22 Dec 2020, Guenter Roeck wrote:
>>> Hi,
>>>
>>> commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
>>> pci_bus_change_irq_level") added sanity checks to the
On Tue, 22 Dec 2020, Guenter Roeck wrote:
On 12/22/20 10:23 AM, Mark Cave-Ayland wrote:
On 22/12/2020 16:16, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to
On Tue, 22 Dec 2020, BALATON Zoltan via wrote:
Hello,
On Tue, 22 Dec 2020, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number
passed
to pci_bus_change_irq_level(). That makes
On 12/22/20 10:23 AM, Mark Cave-Ayland wrote:
> On 22/12/2020 16:16, Guenter Roeck wrote:
>
>> Hi,
>>
>> commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
>> pci_bus_change_irq_level") added sanity checks to the interrupt number passed
>> to pci_bus_change_irq_level(). That
On 22/12/2020 16:16, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count
is indexed and sized by
Hello,
On Tue, 22 Dec 2020, Guenter Roeck wrote:
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count
is indexed and
Hi,
commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in
pci_bus_change_irq_level") added sanity checks to the interrupt number passed
to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count
is indexed and sized by the number of interrupts.
However, as it
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