Re: [PATCH 2/2] CXL/cxl_type3: reset DVSEC CXL Control in ct3d_reset

2024-04-03 Thread Zhijian Li (Fujitsu)
On 03/04/2024 11:42, Li Zhijian wrote: > > > On 02/04/2024 17:17, Jonathan Cameron wrote: >> On Tue,  2 Apr 2024 09:46:47 +0800 >> Li Zhijian wrote: >> >>> After the kernel commit >>> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not >>> match a CFMWS window") >> >>

Re: [PATCH 2/2] CXL/cxl_type3: reset DVSEC CXL Control in ct3d_reset

2024-04-02 Thread Zhijian Li (Fujitsu)
On 02/04/2024 17:17, Jonathan Cameron wrote: > On Tue, 2 Apr 2024 09:46:47 +0800 > Li Zhijian wrote: > >> After the kernel commit >> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not >> match a CFMWS window") > > Fixes tag seems appropriate. > >> CXL type3 devices

Re: [PATCH 2/2] CXL/cxl_type3: reset DVSEC CXL Control in ct3d_reset

2024-04-02 Thread Jonathan Cameron via
On Tue, 2 Apr 2024 09:46:47 +0800 Li Zhijian wrote: > After the kernel commit > 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not > match a CFMWS window") Fixes tag seems appropriate. > CXL type3 devices cannot be enabled again after the reboot because this > flag was