Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS

2023-09-22 Thread Dave Jiang
On 9/22/23 13:08, Michael Tokarev wrote: > 04.09.2023 16:28, Jonathan Cameron: >> From: Dave Jiang >> >> According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth >> Information Structure, if the "Entry Base Unit" is 1024 for BW and the >> matrix entry has the value of 100, the

Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS

2023-09-22 Thread Michael Tokarev
04.09.2023 16:28, Jonathan Cameron: From: Dave Jiang According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth Information Structure, if the "Entry Base Unit" is 1024 for BW and the matrix entry has the value of 100, the BW is 100 GB/s. So the entry_base_unit should be changed

Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS

2023-09-12 Thread Fan Ni
On Mon, Sep 04, 2023 at 02:28:04PM +0100, Jonathan Cameron wrote: > From: Dave Jiang > > According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth > Information Structure, if the "Entry Base Unit" is 1024 for BW and the > matrix entry has the value of 100, the BW is 100 GB/s. So

Re: [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS

2023-09-04 Thread Philippe Mathieu-Daudé
On 4/9/23 15:28, Jonathan Cameron wrote: From: Dave Jiang According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth Information Structure, if the "Entry Base Unit" is 1024 for BW and the matrix entry has the value of 100, the BW is 100 GB/s. So the entry_base_unit should be