On 12/25/21 5:42 PM, liweiwei wrote:
Sorry. In the old spec(version 0.41), nanboxing is not totally disabled, but "NaN-boxing
is limited to |XLEN| bits, not |FLEN| bits". Taking misa.mxl into acount, if misa.mxl is
RV32, and maximum is RV64, this should be sign-extended. Is there any other new
OK. It have been changed to sign-extended in the "processing of Narrower
Values" section of the new spec(version 1.0.0.rc) . I'll fix this and
update other nan-boxing processing in current implementation.
在 2021/12/26 上午9:42, liweiwei 写道:
Sorry. In the old spec(version 0.41), nanboxing is
Sorry. In the old spec(version 0.41), nanboxing is not totally disabled,
but "NaN-boxing is limited to |XLEN| bits, not |FLEN| bits". Taking
misa.mxl into acount, if misa.mxl is RV32, and maximum is RV64, this
should be sign-extended. Is there any other new update for nanboxing to
the spec?
On 12/24/21 7:13 PM, liweiwei wrote:
In RV64 case, this should be nan-boxing value( upper bits are all ones). However, zfinx
will not check nan-boxing of source, the upper 32 bits have no effect on the final result.
So I think both zero-extended or sign-extended are OK.
There is no nanboxing
Thanks for your comments.
在 2021/12/25 上午6:00, Richard Henderson 写道:
On 12/23/21 7:49 PM, liweiwei wrote:
+static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
+{
+ if (ctx->ext_zfinx) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+#ifdef TARGET_RISCV32
+ if
On 12/23/21 7:49 PM, liweiwei wrote:
+static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
+{
+if (ctx->ext_zfinx) {
+switch (get_ol(ctx)) {
+case MXL_RV32:
+#ifdef TARGET_RISCV32
+if (reg_num == 0) {
+tcg_gen_concat_i32_i64(t, ctx->zero,
