On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis
wrote:
>
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c
On Fri, Jul 9, 2021 at 9:06 AM Alistair Francis
wrote:
>
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c
On 7/8/21 8:31 PM, Alistair Francis wrote:
switch (mode) {
case PLICMode_M:
-riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
BOOL_TO_MASK(level));
+if (level) {
+qemu_irq_raise(plic->m_external_irqs[hartid]);
+} else {
+
On 7/9/21 5:31 AM, Alistair Francis wrote:
> Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
> CPU GPIO lines to set the external MIP bits.
>
> Signed-off-by: Alistair Francis
> ---
> include/hw/intc/sifive_plic.h | 4
> hw/intc/sifive_plic.c | 38
