On 2013-11-20 15:47:18 +0100, Michael Matz wrote:
Hi,
On Tue, 19 Nov 2013, Janne Grunau wrote:
+static void handle_fpfpconv(DisasContext *s, uint32_t insn)
+{
+int opcode = get_bits(insn, 16, 3);
+int rmode = get_bits(insn, 20, 2);
rmode is at 19
+case 0x1:
On 21 November 2013 12:34, Janne Grunau j...@jannau.net wrote:
wouldn't make sense to squash that fix into this patch? I'm not used to
the qemu development model but committing patches with already fixed
issues looks strange to me. Unless it's planned to fold the entire patch
series into one
Hi,
On Tue, 19 Nov 2013, Janne Grunau wrote:
+static void handle_fpfpconv(DisasContext *s, uint32_t insn)
+{
+int opcode = get_bits(insn, 16, 3);
+int rmode = get_bits(insn, 20, 2);
rmode is at 19
+case 0x1: /* [S|U]CVTF (scalar-float) */
and it's case 0x0: for
On 2013-09-27 02:48:44 +0200, Alexander Graf wrote:
This patch adds emulation for the instruction group labeled
Floating-point - fixed-point conversions in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf
