Re: [RFC PATCH v3] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

2020-10-17 Thread Philippe Mathieu-Daudé
On 10/16/20 7:28 PM, Richard Henderson wrote: On 10/16/20 6:33 AM, Philippe Mathieu-Daudé wrote: Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or

Re: [RFC PATCH v3] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

2020-10-16 Thread Richard Henderson
On 10/16/20 6:33 AM, Philippe Mathieu-Daudé wrote: > Per "MIPS32 34K Processor Core Family Software User's Manual, > Revision 01.13" page 8 in "Joint TLB (JTLB)" section: > > "The JTLB is a fully associative TLB cache containing 16, 32, >or 64-dual-entries mapping up to 128 virtual pages to