On Fri, 19 Mar 2021 10:47:11 -0700
Ben Widawsky wrote:
> On 21-03-19 18:07:05, Igor Mammedov wrote:
> > On Wed, 17 Mar 2021 14:40:58 -0700
> > Ben Widawsky wrote:
> >
> > > Phil, Igor, Markus
> > >
> > > TL;DR: What to do about multiple capacities in a single device, and what
> > > to do
>
On 21-03-19 18:07:05, Igor Mammedov wrote:
> On Wed, 17 Mar 2021 14:40:58 -0700
> Ben Widawsky wrote:
>
> > Phil, Igor, Markus
> >
> > TL;DR: What to do about multiple capacities in a single device, and what to
> > do
> > about interleave?
> >
> > I've hacked together a basic CXL 2.0
On Wed, 17 Mar 2021 14:40:58 -0700
Ben Widawsky wrote:
> Phil, Igor, Markus
>
> TL;DR: What to do about multiple capacities in a single device, and what to do
> about interleave?
>
> I've hacked together a basic CXL 2.0 implementation which exposes a CXL "Type
> 3"
> memory device (CXL 2.0
On 21-03-17 14:40:58, Ben Widawsky wrote:
> Phil, Igor, Markus
>
> TL;DR: What to do about multiple capacities in a single device, and what to do
> about interleave?
>
> I've hacked together a basic CXL 2.0 implementation which exposes a CXL "Type
> 3"
> memory device (CXL 2.0 Chapter 2.3). For
