IRQ, mmio + IO_DMA_CMD);
> Where and when should the pci_set_master hould be called?
> Thanks,
> Shaked Matzner
>
> From: Peter Maydell
> Sent: Thursday, October 29, 2020 5:46 PM
> To: Shaked Matzner
> Cc: qemu-devel@nongnu.org
> Subject: Re: simple examp
iowrite32(SIZE, mmio +
IO_DMA_CNT);
iowrite32(DMA_CMD | DMA_FROM_DEV
| DMA_IRQ, mmio + IO_DMA_CMD);
Where and when should the pci_set_master hould be called?
Thanks,
Shaked Matzner
From: Peter Maydell
Sent: Thursday, October 29, 2020 5:46 PM
To: Shaked Matzner
Cc: qemu-devel@n
On Thu, 29 Oct 2020 at 14:59, Shaked Matzner wrote:
> however the value I get is still 255(0xff) and not 18(0x12) probably I've
> missed something but when the interrupt is called the transfer to the RAM
> address should be completed, however it seems like the dma_write_buffer
> function from
Hey All,
So I'm trying to learn how pci devices and drivers work using the edu device
and an educational driver, and It seems like the pci_dma_write function fails
to actually write the information from the the dma buffer into the allocated
address in the ram. Here is How I testsed it: 1.I've
