See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 37
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dccd453..bc04a10 100644
---
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 164
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.
Only registers mapped in sregnames or
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/helper.c|4 ++-
target-xtensa/op_helper.c | 26
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 67 +++
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 95
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 508ea1e..72b2099 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4dfca2b..92547d2
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 110 -
1 files
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 14 +++
target-xtensa/translate.c |
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 161
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and at
the new LEND. LEND value at TB compilation time is considered constant
and loop instruction is generated based on this value.
Invalidation may be avoided for the TB at the old LEND address, since
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
Specific xtensa processor overlay for GDB contains register map in
the gdb/xtensa-config.c. This description is used by the GDB to e.g.
parse 'g' response packets and it may be reused in the qemu's gdbstub
(only XTREG definitions for non-pseudoregisters are needed).
Currently mainline GDB does
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644
This series adds support for Tensilica Xtensa target.
Port status: Linux for DC232B works in the qemu.
Not implemented xtensa options: MAC16,
floating point coprocessor, cache option, debug option.
v4 - v5 changes:
- implement boolean option;
- fix v4 stylistical issues (underscores,
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_pic.c | 96
target-xtensa/cpu.h | 45 +-
This is Diamond 232L Standard Core Rev.B (LE).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target |1 +
hw/xtensa_dc232b.c| 116
target-xtensa/gdb-config-dc232b.c | 261 +
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 0aeb7c8..31a6f70
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical
registers.
Window overflow check described in 4.7.1.3 is in
** Patch added: Patch to mips_malta.c
https://bugs.launchpad.net/bugs/842290/+attachment/2359348/+files/malta.patch
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You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/842290
Title:
MIPS Malta
Public bug reported:
One of the hardcoded bootloader library instructions in the MIPS Malta
mini-bootloader's print function is:
stl_raw(p++, 0x08000205); /* j 814
*/
Since this function is loaded at 0xbfc00808, this jump jumps to the
middle of nowhere. The
At 09/04/2011 04:25 PM, Avi Kivity Write:
On 09/02/2011 05:56 AM, Wen Congyang wrote:
You could use something like kvm-unit-tests.git to write a simple test
that sets up a BAR (say from hw/ivshmem.c), writes and reads to see
that
it is visible, programs the bridge to filter part of
On Mon, Sep 05, 2011 at 12:19:46PM +0300, Michael S. Tsirkin wrote:
On Mon, Sep 05, 2011 at 02:43:16PM +1000, David Gibson wrote:
On Sun, Sep 04, 2011 at 12:16:43PM +0300, Michael S. Tsirkin wrote:
On Sun, Sep 04, 2011 at 12:46:35AM +1000, David Gibson wrote:
On Fri, Sep 02, 2011 at
Hi, all
I am trying to figure out how QEMU manages the guest machine's memory. If I
understand correctly, QEMU uses RAMBlock as a unit when it allocates guest
machine's memory. All RAMBlocks are maintained in RAMList. Guest machine needs
to call qemu_ram_alloc first to get a RAMBlock, then call
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