This patch adds multiqueue support for tap device by allowing multiple
sockets to be attached to a tap device. Then we could parallize packets
transmission/reception by put them into different socket.
Following steps were used when choose tx queues:
1 For the packets comes from multiqueue nics,
New ioctls were added to let multiple files/sockets to be attached to
a tap device.
Signed-off-by: Jason Wang jasow...@redhat.com
---
drivers/net/tun.c | 25 ++---
include/linux/if_tun.h |3 +++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git
At Fri, 16 Sep 2011 16:25:40 +0200,
Paolo Bonzini wrote:
Outside coroutines, avoid busy waiting on EAGAIN by temporarily
making the socket blocking.
The API of qemu_recvv/qemu_sendv is slightly different from
do_readv/do_writev because they do not handle coroutines. It
returns the number
At Fri, 16 Sep 2011 16:25:41 +0200,
Paolo Bonzini wrote:
When the other side is shutdown, read returns zero (writes return EPIPE).
In this case, care must be taken to avoid infinite loops. This error
was already present in sheepdog.
Cc: MORITA Kazutaka morita.kazut...@lab.ntt.co.jp
On Fri, Sep 16, 2011 at 05:53:20PM +0200, Christoph Hellwig wrote:
On Wed, Sep 14, 2011 at 04:50:25PM +0100, Stefan Hajnoczi wrote:
I think in this case it will not make the code nicer. Since the
external iSCSI library is based on callbacks it would be necessary to
write the
It was introduced with commit 54936004fddc52c321cb3f9a9a51140e782bed5d
as host_page_bits but never used.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
cpu-all.h |1 -
exec.c|4
2 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index
Am 05.09.2011 11:06, schrieb Stefan Weil:
The number of registers needed for the return value of TCG opcode
INDEX_op_call is calculated in function tcg_gen_callN (nb_rets).
It can be 0 or 1, for 32 bit hosts also 2 (return 64 bit value in
two 32 bit registers).
Some TCG implementations reserve
On 09/17/2011 08:29 AM, MORITA Kazutaka wrote:
+#else
+struct iovec *p = iov;
+ret = 0;
+while (iovlen 0) {
+int rc;
+if (do_sendv) {
+rc = send(sockfd, p-iov_base, p-iov_len, 0);
+} else {
+
On 17 September 2011 02:08, andrzej zaborowski balr...@gmail.com wrote:
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -284,7 +284,7 @@ static void omap_gpmc_write(void *opaque,
target_phys_addr_t addr,
break;
case 0x018: /* GPMC_IRQSTATUS */
- s-irqen = ~value;
+
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
We have a qemu internal abstraction layer on FDT. While I'm not fully
convinced
we need it at all, it's missing the nop_node functionality that we now need
on e500. So let's add it and think about the general future of that
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
CPUs that are not the boot CPU need to run in spinning code to check if they
should run off to execute and if so where to jump to. This usually happens
by leaving secondary CPUs looping and checking if some variable in memory
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
This patch updates the kvm kernel headers to the latest version.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h | 23 +++
linux-headers/asm-x86/kvm_para.h | 14
On Wed, Sep 14, 2011 at 8:43 AM, Alexander Graf ag...@suse.de wrote:
From: David Gibson da...@gibson.dropbear.id.au
This patch implements support for the CFAR SPR on POWER7 (Come From
Address Register), which snapshots the PC value at the time of a branch or
an rfid. The latest powerpc-next
Am 17.09.2011 um 18:58 schrieb Blue Swirl blauwir...@gmail.com:
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
CPUs that are not the boot CPU need to run in spinning code to check if they
should run off to execute and if so where to jump to. This usually happens
by
At Sat, 17 Sep 2011 16:49:22 +0200,
Paolo Bonzini wrote:
On 09/17/2011 08:29 AM, MORITA Kazutaka wrote:
+#else
+struct iovec *p = iov;
+ret = 0;
+while (iovlen 0) {
+int rc;
+if (do_sendv) {
+rc =
Am 17.09.2011 um 18:59 schrieb Blue Swirl blauwir...@gmail.com:
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
This patch updates the kvm kernel headers to the latest version.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-headers/asm-powerpc/kvm.h | 23
On Sat, Sep 17, 2011 at 5:15 PM, Alexander Graf ag...@suse.de wrote:
Am 17.09.2011 um 18:58 schrieb Blue Swirl blauwir...@gmail.com:
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf ag...@suse.de wrote:
CPUs that are not the boot CPU need to run in spinning code to check if they
should run
On Fri, Sep 16, 2011 at 4:00 PM, Anthony Liguori aligu...@us.ibm.com wrote:
By using a prefix of :: in the name, we can safely derive the composed
device
name from the parent device and busses name. For instance, if the ::i440fx
device created a device named piix3, it would look like this:
On Fri, Sep 16, 2011 at 4:00 PM, Anthony Liguori aligu...@us.ibm.com wrote:
This series introduces an infrastructure to remove anonymous devices from
qdev.
Anonymous devices are one of the big gaps between qdev and QOM so removing is
a prerequisite to incrementally merging QOM.
Besides the
Thanks, applied.
On Fri, Sep 16, 2011 at 7:50 PM, Stefan Weil w...@mail.berlios.de wrote:
make -C mybuilddir no longer works (regression caused by commit)
388d475815c23901010a25c845eb078d47ee0740.
PWD is the directory of the caller (not mybuilddir),
so BUILD_DIR is set to the wrong value.
Thanks, applied all.
On Tue, Sep 13, 2011 at 12:34 PM, Stefan Hajnoczi
stefa...@linux.vnet.ibm.com wrote:
This series removes the tracetool parser limitation that format strings must
begin and end with double quotes. In practice this means we need to work
around PRI*64 usage by adding dummy
Thanks, applied.
On Fri, Sep 16, 2011 at 3:29 PM, Max Reitz m...@tyndur.org wrote:
haddp[sd], hsubp[sd] and addsubp[sd] operate on floats, thus it is
necessary to use the appropriate floating point calculation functions.
If this is not done, those functions operate merely on integers, which
Thanks, applied all.
On Sat, Sep 17, 2011 at 2:01 PM, Stefan Weil w...@mail.berlios.de wrote:
Am 05.09.2011 11:06, schrieb Stefan Weil:
The number of registers needed for the return value of TCG opcode
INDEX_op_call is calculated in function tcg_gen_callN (nb_rets).
It can be 0 or 1, for 32
Writing to IRQSTATUS should affect irqst, not irqen -- error
spotted by Andrzej Zaborowski.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/omap_gpmc.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index e27b93c..7fc82a2
Promote the remark about why we handle FIFOTHRESHOLDSTATUS the
way we do from the commit message of de8af7fe0 to a comment in
the code.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/omap_gpmc.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git
Le jeudi 15 septembre 2011 à 08:06 +0200, Paolo Bonzini a écrit :
On 09/14/2011 06:36 PM, Orit Wasserman wrote:
I think NBD would be fine, especially with a flush command.
I think NBD would be fine, especially with a flush command.
If I remember correctly , there is a problem with NBD
On Sat, Sep 17, 2011 at 02:02:04PM +0800, Jason Wang wrote:
A wiki-page was created to narrate the detail design of all parts
involved in the multi queue implementation:
http://www.linux-kvm.org/page/Multiqueue and some basic tests result
could be seen in this page
On Fri, Sep 16, 2011 at 12:46:40PM -0400, Stefan Berger wrote:
On 09/16/2011 10:44 AM, Michael S. Tsirkin wrote:
On Thu, Sep 15, 2011 at 10:33:13AM -0400, Stefan Berger wrote:
On 09/15/2011 08:28 AM, Michael S. Tsirkin wrote:
So the below is a proposal for a directory scheme
for storing
Add a monitor command 'info mtree' to show the memory hierarchy
much like /proc/iomem in Linux.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
v1-v2: use /proc/iomem format.
---
memory.c | 27 +++
memory.h |2 ++
monitor.c |7 +++
3 files changed, 36
Since we use memory API in sun4u.c, after
71579cae30b53c910cd6c47ab4e683f647d36519, setting up isa_mem_base
puts vga.chain4 outside of the physical address space.
Fix by removing obsolete isa_mem_base set up.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
hw/sun4u.c |1 -
1 files
Hello,
these patches add a new code generator (TCG target) to qemu.
Unlike other tcg target code generators, this one does not generate
machine code for some cpu. It generates machine independent bytecode
which is interpreted later. That's why I called it TCI (tiny code
interpreter).
I wrote
Tests of the tcg interpreter on an (emulated) ppc host
needed this small change.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
cache-utils.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/cache-utils.h b/cache-utils.h
index 0b65907..7c3b282 100644
---
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/tcg.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bdd7a67..30f3aef 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -794,7 +794,9 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
Makefile.target |1 +
configure | 30 --
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index 88d2f1f..a2c3a4a 100644
--- a/Makefile.target
+++
TCG_TARGET_REG_BITS can be determined by the compiler,
so there is no need to declare it for each individual tcg target.
This is especially important for new tcg targets
which will be supported by the tcg interpreter.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/tcg.h | 10
Unlike other tcg target code generators, this one does not generate
machine code for some cpu. It generates machine independent bytecode
which is interpreted later.
This allows running QEMU on any host.
Interpreted bytecode is slower than direct execution of generated
machine code.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/tcg.h |4 +-
tcg/tci.c | 1200 +
2 files changed, 1203 insertions(+), 1 deletions(-)
create mode 100644 tcg/tci.c
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 1859fae..c99c7ea
It is now declared for all tcg targets in tcg.h,
so the tcg target specific declarations are redundant.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/arm/tcg-target.h |1 -
tcg/hppa/tcg-target.h |4 +---
tcg/ia64/tcg-target.h |2 --
tcg/mips/tcg-target.h |1 -
These functions are defined in the tcg target specific file
tcg-target.c.
The forward declarations assert that every tcg target uses
the same function prototype.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
tcg/tcg.c | 16
1 files changed, 16 insertions(+), 0
On 17 September 2011 21:00, Stefan Weil w...@mail.berlios.de wrote:
Tests of the tcg interpreter on an (emulated) ppc host
needed this small change.
Signed-off-by: Stefan Weil w...@mail.berlios.de
---
cache-utils.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
Am 17.09.2011 23:31, schrieb Peter Maydell:
On 17 September 2011 21:00, Stefan Weilw...@mail.berlios.de wrote:
Tests of the tcg interpreter on an (emulated) ppc host
needed this small change.
Signed-off-by: Stefan Weilw...@mail.berlios.de
---
cache-utils.h |2 +-
1 files changed, 1
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivity a...@redhat.com wrote:
On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote:
Sure :). So the problem is that when emulating the G3 Beige machine in
QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently,
on x86 that PCI VGA
On 17 September 2011 21:00, Stefan Weil w...@mail.berlios.de wrote:
+/* Forward declarations for functions declared and used in tcg-target.c. */
+static int target_parse_constraint(TCGArgConstraint *ct, const char
**pct_str);
+static void tcg_out_ld(TCGContext *s, TCGType type, int ret, int
The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.
-Original Message-
From: qemu-devel-bounces+ericj=mips@nongnu.org
[mailto:qemu-devel-bounces+ericj=mips@nongnu.org] On Behalf Of Eric Johnson
Sent: Saturday, September 17, 2011 5:06 PM
To: qemu-devel@nongnu.org;
The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This
is required for AVPs to pass.
Signed-off-by: Eric Johnson er...@mips.com
---
When MIPS_DEBUG_DISAS is defined the gen_logic_imm, gen_slt_imm,
gen_cond_move, gen_logic and gen_slt functions cause errors because ctx
is not defined. Fixed the functions by passing in the DisasContext.
Signed-off-by: Eric Johnson er...@mips.com
---
target-mips/translate.c | 72
Stefan Weil w...@mail.berlios.de writes:
+
+switch (opc) {
+case INDEX_op_end:
+case INDEX_op_nop:
+break;
You could probably get some more speed out of this by using a threaded
interpreter with gcc's computed goto extension. That's typically
significantly
Am 18.09.2011 06:03, schrieb Andi Kleen:
Stefan Weil w...@mail.berlios.de writes:
+
+ switch (opc) {
+ case INDEX_op_end:
+ case INDEX_op_nop:
+ break;
You could probably get some more speed out of this by using a threaded
interpreter with gcc's computed goto extension. That's typically
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