The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It also has 802.1Q VLAN
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |2 +
hw/arm/faraday.h | 64
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we emulate only the SDRAM enable function.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |4 ++
hw/arm/ftddrii030.c | 170
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel starts transfers. Each
It's used to perform AHB remap and QEMU RAM initialization
when the SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |4 +
hw/arm/ftahbc020.c| 190
The BIT6 of Status Register(SR):
SR[6] behaves the same as R/B# pin
SR[6] = 0 indicates the device is busy;
SR[6] = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or error timeout.
P.S:
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
the system by
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the hardware handshake
The FTI2C010 is a simple I2C master controller.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |6 ++
hw/arm/fti2c010.c | 216 +
hw/arm/fti2c010.h | 71
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm function. When the
The s-addr should be reset along with the s-addrlen,
or it might have the previous address shifted to MSB
and then causes problem to nand erase operation.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/nand.c |1 +
1 file changed, 1 insertion(+)
diff --git a/hw/nand.c b/hw/nand.c
index
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
include/qemu/bitops.h | 63 -
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..920d028 100644
--- a/include/qemu/bitops.h
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional hardware ECC function
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday.h
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or color value
2. an
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |7 +
hw/arm/ftsdc010.c | 358
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer for Linux. However it
- Original Message -
On 03/05/13 22:08, Eric Blake wrote:
On 03/04/2013 03:19 PM, Laszlo Ersek wrote:
Signed-off-by: Laszlo Ersek ler...@redhat.com
---
+# @guest-set-vcpus:
+#
+# Attempt to reconfigure (currently: enable/disable) logical
processors inside
+# the
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic sampling
method to
The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su dant...@gmail.com
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 ++
hw/arm/ftpwmtmr010.c | 264 +
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