On 10/08/2015 04:09 PM, Peter Crosthwaite wrote:
> On Thu, Oct 8, 2015 at 8:40 AM, Michael Davidsaver
> wrote:
>> Implement the SYSRESETREQ bit of the AIRCR register
>> for armv7-m (ie. cortex-m3).
>>
>
> This would serve better as the commit message to the patch (which I
On Thu, 10/01 15:13, Kevin Wolf wrote:
> This simplifies the code somewhat, especially when dropping whole
> backing file subchains.
>
> The exception is the mirroring code that does adventurous things with
> bdrv_swap() and in order to keep it working, I had to duplicate most of
>
On Thu, 10/01 15:13, Kevin Wolf wrote:
> bdrv_swap() has always been an ugly hack that we would rather have
> avoided. When it was introduced, we simply didn't have the
> infrastructure to update pointers instead of transplanting the contents
> of BDS object, so we grudgingly added bdrv_swap() as
From: Paolo Bonzini
This file does not exist on bionic libc and the functions it defines
are in fact not used by pci-assign.c. Remove it.
Reported-by: Houcheng Lin
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael Tokarev
When CONFIG_LINUX is off, devices "virtio-keyboard-device",
"virtio-mouse-device", "virtio-tablet-device" and
"virtio-input-host-device" aren't compiled in, yet
"virtio-keyboard-pci", "virtio-mouse-pci", "virtio-tablet-pci" and
"virtio-input-host-pci" still are. Attempts to introspect them crash,
On 10/09/2015 05:53 AM, David Kiarie wrote:
From: David
Introduce basic AMD IOMMU emulation in Qemu. IOMMU implements event logging and
host translation which should allow nested PCI passthrough.It also implemented
a very basic IOTLB implementation
Signed-off-by: David
* Wen Congyang (we...@cn.fujitsu.com) wrote:
> On 10/08/2015 03:00 AM, Dr. David Alan Gilbert wrote:
> > * Wen Congyang (we...@cn.fujitsu.com) wrote:
> >> In some cases, we want to take a quorum child offline, and take
> >> another child online.
> >
> > Hi,
> > Have you checked the output of
On 28 September 2015 at 16:31, Andrew Jones wrote:
> On Thu, Sep 24, 2015 at 12:13:08PM +0200, Andrew Jones wrote:
>> On Wed, Sep 23, 2015 at 08:43:39AM -0700, Peter Maydell wrote:
>> > On 23 September 2015 at 07:18, Andrew Jones wrote:
>> > > ARM/AArch64
On 28 September 2015 at 11:07, Sergey Fedorov wrote:
> A QEMU breakpoint match is not definitely an architectural breakpoint
> match. If an exception is generated unconditionally during translation,
> it is hardly possible to ignore it in the debug exception handler.
>
>
On 6 October 2015 at 20:47, Davorin Mista wrote:
> Added oslar_write function to OSLAR_EL1 sysreg, using a status variable
> in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked
> to the newly added read-only OSLSR_EL1 register.
>
> Linux reads from this
Signed-off-by: Michael Davidsaver
---
hw/intc/armv7m_nvic.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 3ec8408..a671d84 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -15,6
Implement the SYSRESETREQ bit of the AIRCR register
for armv7-m (ie. cortex-m3).
A small patch to see if I have the submission process figured out.
Michael Davidsaver (1):
armv7-m: exit on external reset request
hw/intc/armv7m_nvic.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
From: "Dr. David Alan Gilbert"
Newer GLib's want unique test paths, and thus moan at dupes.
(Seen on Fedora 23 which has glib 2.46)
Uniquify the paths.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Eric Blake
Signed-off-by:
On Wed, Oct 07, 2015 at 05:24:27PM +0100, Alex Bennée wrote:
>
> Edgar E. Iglesias writes:
>
> > From: "Edgar E. Iglesias"
> >
> > Introduce ARMMMUFaultInfo to propagate MMU Fault information
> > across the MMU translation code path. This is
There are a couple of spots in the QEMU code which use g_malloc0,
directly followed by a memset or memcpy which fill the whole
allocated buffer. In this case it either does not make sense to
zero the buffer via g_malloc0 first (so g_malloc should be used
instead), or if the second command is a
g_malloc0 already clears the memory, so no need for
the additional memset here.
Cc: Paolo Bonzini
Cc: David Gibson
Cc: Alexander Graf
Signed-off-by: Thomas Huth
---
hw/scsi/spapr_vscsi.c | 1 -
1 file changed,
On Wed, Oct 07, 2015 at 01:24:27PM +0100, Alex Bennée wrote:
>
> Edgar E. Iglesias writes:
>
> > From: "Edgar E. Iglesias"
> >
> > The starting level for S2 pagetable walks is computed
> > differently from the S1 starting level. Implement
When there are many instances of a given class, registering
properties against the instance is wasteful of resources. The
majority of objects have a statically defined list of possible
properties, so most of the properties are easily registerable
against the class. Only those properties which are
On 6 October 2015 at 18:43, Sergey Sorokin wrote:
> That is ok.
Thanks; I've now applied your patch to target-arm.next and sent
out the patch to fix the no-64-bit-EL2 assumptions in the code.
-- PMM
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