[Qemu-devel] [PULL 18/21] target-mips: make ITC Configuration Tags accessible to the CPU

Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 29/03/16 00:21, Paolo Bonzini wrote: > > On 28/03/2016 17:18, Sergey Fedorov wrote: >> The use pattern of 'tb_invalidated_flag' is a bit intricate; correct me, >> if I'm wrong about the following. Basically, 'tb_invalidated_flag' was >> meant to catch two events: >> * some TB has been

[Qemu-devel] [PULL 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views

P/V Synchronized and Try Views can be used to access Semaphore cells. Load returns current value and post-decrements the value in the cell (until it reaches zero). Stores increment the value (until it saturates at 0x). P/V Synchronized View causes the issuing thread to block on read if value

[Qemu-devel] [PULL 16/21] hw/mips: implement ITC Storage - Bypass View

Bypass View does not cause issuing thread to block and does not affect any of the cells state bit. Read from a FIFO cell returns the value of the oldest entry. Store to a FIFO cell changes the value of the newest entry. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c |

[Qemu-devel] [PULL 00/21] target-mips queue for 2.6

:24:02 +) are available in the git repository at: git://github.com/lalrae/qemu.git tags/mips-20160329 for you to fetch changes up to e9f517b73dab520de05b871359d2beedf8b04e53: target-mips: add MAAR, MAARI register (2016-03-28 19

[Qemu-devel] [PULL 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0

From: Yongbok Kim Reuse CP0_CHECK macro for gen_m{f|t}hc0. Signed-off-by: Yongbok Kim Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate.c | 46

[Qemu-devel] [PULL 02/21] target-mips: add CMGCRBase register

From: Yongbok Kim Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Signed-off-by: Yongbok Kim

[Qemu-devel] [PULL 13/21] hw/mips: implement ITC Storage - Control View

Control view is used to access the ITC Storage Cell Tags. It never causes the issuing thread to block. Guest can empty the FIFO cell by setting Empty bit to 1. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c | 104 + 1

[Qemu-devel] [PULL 03/21] hw/mips: add initial Global Config Register support

From: Yongbok Kim Add initial GCR support to indicate number of VPs present in the system, L2 bypass mode and revision number. Signed-off-by: Yongbok Kim [leon.al...@imgtec.com: * removed GIC part, * changed commit message, * replaced %lx

[Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init

Global smp_cpus is never zero (even if user provides -smp 0), thus clocks and irqs are always initialized for each created CPU in the loop at the beginning of mips_malta_init. These two lines cause a leak of already allocated timer and irqs for the first CPU - remove them. Signed-off-by: Leon

[Qemu-devel] [PULL 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader()

Remove CPUMIPSState from the write_bootloader() argument list as it is not used in the function. Signed-off-by: Leon Alrae --- hw/mips/mips_malta.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c

[Qemu-devel] [PULL 10/21] hw/mips_malta: add CPS to Malta board

If the user specifies smp > 1 and the CPU with CM GCR support, then create Coherent Processing System (which takes care of instantiating CPUs) rather than CPUs directly and connect i8259 and cbus to the pins exposed by CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use the

[Qemu-devel] [PULL 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6

Signed-off-by: Leon Alrae --- target-mips/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index a5b8805..65f2caf 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17194,6 +17194,7 @@

[Qemu-devel] [PULL 05/21] hw/mips: add initial Cluster Power Controller support

Cluster Power Controller (CPC) is responsible for power management in multiprocessing system. It provides registers to control the power and the clock frequency of the individual elements in the system. This patch implements only three registers that are used to control the power state of each VP

[Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views

Empty/Full Synchronized and Try views can be used to access FIFO cells. Store to the FIFO cell pushes the value into the queue, load pops the oldest element from the queue. Cell's Full and Empty bits are automatically updated to reflect new state of the cell. Empty/Full Synchronized View causes

[Qemu-devel] [PULL 06/21] hw/mips/cps: create CPC block inside CPS

Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest

[Qemu-devel] [PULL 19/21] hw/mips/cps: enable ITU for multithreading processors

Make ITU available in the system if CPU supports multithreading and is part of CPS. Signed-off-by: Leon Alrae --- hw/mips/cps.c | 32 include/hw/mips/cps.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/hw/mips/cps.c

[Qemu-devel] [PULL 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU

Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-mips/translate_init.c

Re: [Qemu-devel] [PATCH] smbios: fix typo

sorry mjt, I intended to cc qemu-trivial, now I made it:) On 03/29/2016 05:48 PM, Cao jin wrote: The spec says: "on paragraph (16-byte) boundaries" Signed-off-by: Cao jin --- include/hw/smbios/smbios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [Qemu-devel] [PATCH] exec.c: Ensure right alignment also for file backed ram

On 29/03/2016 11:29, Dominik Dingel wrote: >> > Why is this part necessary? On x86 you can have 1 megabyte of RAM, >> > but QEMU_VMALLOC_ALIGN is 2MB. > You are right, I changed this to keep the change consistent and thought > the use case of x86 guests with 1 MB RAM might be a little bit

[Qemu-devel] [PATCH] smbios: fix typo

The spec says: "on paragraph (16-byte) boundaries" Signed-off-by: Cao jin --- include/hw/smbios/smbios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/smbios/smbios.h b/include/hw/smbios/smbios.h index 76ccf70..ba36746 100644 ---

Re: [Qemu-devel] [Nbd] [PATCH 2/2] NBD proto: add GET_LBA_STATUS extension

Am 24.03.2016 um 17:47 hat Wouter Verhelst geschrieben: > On Thu, Mar 24, 2016 at 05:07:47PM +0100, Kevin Wolf wrote: > > Am 24.03.2016 um 17:04 hat Eric Blake geschrieben: > > > On 03/24/2016 09:53 AM, Wouter Verhelst wrote: > > > > On Thu, Mar 24, 2016 at 04:33:42PM +0100, Paolo Bonzini wrote: >

Re: [Qemu-devel] [PATCH] exec.c: Ensure right alignment also for file backed ram

On Thu, 24 Mar 2016 12:35:10 +0100 Paolo Bonzini wrote: > > > On 23/03/2016 22:32, Dominik Dingel wrote: > > -page_size = qemu_fd_getpagesize(fd); > > -block->mr->align = page_size; > > +alignment = MAX(qemu_fd_getpagesize(fd), QEMU_VMALLOC_ALIGN); > > +

Re: [Qemu-devel] [Qemu-block] [PATCH v6 00/11] Add new LUKS block driver (for 2.6)

On Tue, Mar 29, 2016 at 11:13:55AM +0200, Kevin Wolf wrote: > Am 23.03.2016 um 14:53 hat Kevin Wolf geschrieben: > > Am 21.03.2016 um 15:11 hat Daniel P. Berrange geschrieben: > > > This series is just the block layer parts needed to add > > > a LUKS driver to QEMU. It was previously posted as

Re: [Qemu-devel] [PATCH 0/6] virtio: refactor host notifiers

On 29/03/2016 10:18, Cornelia Huck wrote: >> > >> > Tested-by: Paolo Bonzini >> > >> > Resisted 6 minutes versus 10 seconds. At about 2.5 seconds per reboot, >> > that means the failure happened at the fourth reboot before, and >> > resisted about 150 reboots with your

Re: [Qemu-devel] [PATCH 0/6] virtio: refactor host notifiers

Hi Paolo: On 03/29/2016 02:11 AM, Paolo Bonzini wrote: On 28/03/2016 05:55, TU BO wrote: Hi Cornelia: I got two crash with qemu master + "[PATCH 0/6] virtio: refactor host notifiers", Hi Tu Bo, please always include the assertion patch at

Re: [Qemu-devel] [Qemu-block] [PATCH v6 00/11] Add new LUKS block driver (for 2.6)

Am 23.03.2016 um 14:53 hat Kevin Wolf geschrieben: > Am 21.03.2016 um 15:11 hat Daniel P. Berrange geschrieben: > > This series is just the block layer parts needed to add > > a LUKS driver to QEMU. It was previously posted as part > > of the larger series > > > > v1:

Re: [Qemu-devel] [PULL v3 02/13] crypto: add support for PBKDF2 algorithm

On Thu, Mar 24, 2016 at 11:06:21AM +0800, Wen Congyang wrote: > On 03/18/2016 12:53 AM, Daniel P. Berrange wrote: > > The LUKS data format includes use of PBKDF2 (Password-Based > > Key Derivation Function). The Nettle library can provide > > an implementation of this, but we don't want code

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 29/03/2016 10:14, Paolo Bonzini wrote: > > > On 29/03/2016 00:12, Richard Henderson wrote: >>> There is also a case where a TB jumps to itself; it then appears twice >>> in the list with different values in the low bits, such as this: >>> >>> tb->jmp_list_first = tb | 0; >>>

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 29/03/16 01:12, Richard Henderson wrote: > On 03/24/2016 08:11 AM, Paolo Bonzini wrote: >> There is also a case where a TB jumps to itself; it then appears twice >> in the list with different values in the low bits, such as this: >> >> tb->jmp_list_first = tb | 0; >>

Re: [Qemu-devel] [Nbd] [PATCH 3/1] doc: Propose Structured Replies extension

On 29 Mar 2016, at 04:56, Eric Blake wrote: > The existing transmission phase protocol is difficult to sniff, > because correct interpretation of the server stream requires > context from the client stream (or risks false positives if > data payloads happen to contain the

Re: [Qemu-devel] [PATCH 0/6] virtio: refactor host notifiers

On Thu, 24 Mar 2016 18:06:21 +0100 Paolo Bonzini wrote: > On 24/03/2016 17:15, Cornelia Huck wrote: > > Here's the next version of my refactoring of the virtio host notifiers. > > This one actually survives a bit of testing for me (reboot loop). > > > > As this patchset

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 29/03/2016 00:12, Richard Henderson wrote: >> There is also a case where a TB jumps to itself; it then appears twice >> in the list with different values in the low bits, such as this: >> >> tb->jmp_list_first = tb | 0; >> .' | >> |

Re: [Qemu-devel] [PATCH RFC 00/14] vhost-user: shutdown and reconnection

On Fri, Mar 25, 2016 at 07:00:15PM +0100, Marc-André Lureau wrote: > Hi > > On Thu, Mar 24, 2016 at 8:10 AM, Yuanhan Liu > wrote: > >> > The following series starts from the idea that the slave can request a > >> > "managed" shutdown instead and later recover (I

Re: [Qemu-devel] [RESEND PATCH v2 0/4] QOM'ify hw/audio files

At 2016-03-17 17:06:12, "xiaoqiang zhao" wrote: >This patch set QOM'ify some files under hw/audio directory. >See each patch's commit message for details. > >Changes in v2: >Move AUD_open_in/out function into device realize stage > >Sorry for the misoperation before, so I

[Qemu-devel] [PATCH v2 3/6] hw/char: QOM'ify lm32_juart.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/char/lm32_juart.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/char/lm32_juart.c b/hw/char/lm32_juart.c index 5bf8acf..cd8d0ee 100644 ---

Re: [Qemu-devel] [RFC 2/7] virtio: stop virtqueue processing if device is broken

On Thu, 24 Mar 2016 17:56:49 + Stefan Hajnoczi wrote: > QEMU prints an error message and exits when the device enters an invalid > state. Terminating the process is heavy-handed. The guest may still be > able to function even if there is a bug in a virtio guest driver.

[Qemu-devel] [PATCH v2 1/6] hw/char: QOM'ify escc.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/char/escc.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 7bf09a0..b802c3e 100644 --- a/hw/char/escc.c +++

[Qemu-devel] [PATCH v2 5/6] hw/char: QOM'ify sclpconsole-lm.c

Drop the DO_UPCAST macro Signed-off-by: xiaoqiang zhao --- hw/char/sclpconsole-lm.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/char/sclpconsole-lm.c b/hw/char/sclpconsole-lm.c index 7d4ff81..a22ad8d 100644 ---

[Qemu-devel] [PATCH v2 6/6] hw/char: QOM'ify sclpconsole.c

Drop the DO_UPCAST macro Signed-off-by: xiaoqiang zhao --- hw/char/sclpconsole.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c index 45997ff..15a5b2b 100644 --- a/hw/char/sclpconsole.c +++

[Qemu-devel] [PATCH v2 4/6] hw/char: QOM'ify lm32_uart.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/char/lm32_uart.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c index 036813d..f29054b 100644 ---

[Qemu-devel] [PATCH v2 2/6] hw/char: QOM'ify etraxfs_ser.c

Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao --- hw/char/etraxfs_ser.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 146b387..ede7024 100644 ---

[Qemu-devel] [PATCH v2 0/6] QOM'ify hw/char devices

This patch set trys to QOM'ify hw/char files, see commit messages for more details Changes in v2: * rename TYPE_SCLP_LM_CONSOLE to TYPE_SCLPLM_CONSOLE which is suggested by Cornelia Huck * rebase on the current master xiaoqiang zhao (6): hw/char: QOM'ify escc.c

Re: [Qemu-devel] [Nbd] [PATCH 3/3] NBD proto: add "Command flags" section

On Mon, Mar 28, 2016 at 07:45:27AM -0600, Eric Blake wrote: > On 03/28/2016 04:43 AM, Denis V. Lunev wrote: > > From: Pavel Borzenkov > > > > Add separate "Command flags" section to make it clear which flags are > > currently defined by the protocol. > > > >

Re: [Qemu-devel] [Nbd] [PATCH 3/1] doc: Propose Structured Replies extension

Hi Eric, After applying some of the other outstanding patches, this one doesn't apply anymore. Can you rebase? On Mon, Mar 28, 2016 at 09:56:36PM -0600, Eric Blake wrote: > The existing transmission phase protocol is difficult to sniff, > because correct interpretation of the server stream

Re: [Qemu-devel] [Nbd] [PATCH 1/3] NBD proto: forbid TRIM command without negotiation

On Mon, Mar 28, 2016 at 07:00:17AM -0600, Eric Blake wrote: > On 03/28/2016 04:43 AM, Denis V. Lunev wrote: > > From: Pavel Borzenkov > > > > There is a loophole in the protocol that allows a client to send TRIM > > request even if support for it wasn't negotiated with

Re: [Qemu-devel] [Qemu-ppc] [PATCH] spapr: compute interrupt vector address from LPCR

On 03/25/2016 12:45 PM, Greg Kurz wrote: > Hi Cedric, > > On Thu, 24 Mar 2016 16:28:53 +0100 > Cédric Le Goater wrote: > >> This address is changed by the linux kernel using the H_SET_MODE hcall >> and needs to be migrated in order to restart a spapr VM running in >> TCG. This

Re: [Qemu-devel] [PATCH] doc: Mention proper use of handle

On Mon, Mar 28, 2016 at 07:59:15AM -0600, Eric Blake wrote: > Although the proper use of the handle field during transmission > phase was implied, it never hurts to make it more explicit that > clients should alter the handle on each message, and the server > repeat the handle unchanged, in order

Re: [Qemu-devel] [PATCH qemu v14 17/18] vfio/spapr: Use VFIO_SPAPR_TCE_v2_IOMMU

On Tue, Mar 29, 2016 at 04:44:04PM +1100, Alexey Kardashevskiy wrote: > On 03/29/2016 04:30 PM, David Gibson wrote: > >On Thu, Mar 24, 2016 at 08:10:44PM +1100, Alexey Kardashevskiy wrote: > >>On 03/24/2016 11:03 AM, Alexey Kardashevskiy wrote: > >>>On 03/23/2016 05:03 PM, David Gibson wrote: >

Re: [Qemu-devel] [Qemu-ppc] [PATCHv2 2/3] target-ppc: Add helpers for updating a CPU's SDR1 and external HPT

On Fri, Mar 25, 2016 at 10:13:59AM +0100, Greg Kurz wrote: > Hi Laurent, > > On Thu, 24 Mar 2016 09:41:59 +0100 > Laurent Vivier wrote: > > > On 24/03/2016 06:35, David Gibson wrote: > > > On Tue, Mar 22, 2016 at 05:33:45PM +0100, Laurent Vivier wrote: > > >> Hi David, > >

Re: [Qemu-devel] [PATCH qemu v14 18/18] spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)

On 03/29/2016 04:22 PM, David Gibson wrote: On Thu, Mar 24, 2016 at 01:32:48PM +1100, Alexey Kardashevskiy wrote: On 03/23/2016 05:11 PM, David Gibson wrote: On Wed, Mar 23, 2016 at 02:28:01PM +1100, Alexey Kardashevskiy wrote: On 03/23/2016 01:13 PM, David Gibson wrote: On Mon, Mar 21, 2016

<    1   2   3   4