[Qemu-devel] [RFC PATCH 0/2] Support building qemu-user powered docker test images

Hi, I had a an set of scripts for setting up and running executable binaries in a $arch-linux-user powered rootfs. However it has been a while since I last used them and there was various breakage which spurred me on to a better way. As Fam has been working with Docker containers for building I

[Qemu-devel] [RFC PATCH 1/2] tests/docker/docker.py: support --qemu option

When passed the name of a qemu-$arch binary we copy it and any linked libraries into the docker build context. These can then be included by a dockerfile with the line: # Copy all of context into container ADD . / Signed-off-by: Alex Bennée ---

[Qemu-devel] [PATCH] hw/intc/gic: RAZ/WI non-sec access to sec interrupts

Treat non-secure accesses to registers and bits in registers of secure interrupts as RAZ/WI. Signed-off-by: Jens Wiklander --- hw/intc/arm_gic.c | 68 ++- 1 file changed, 62 insertions(+), 6 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] hw/arm/virt: Reject gic-version=host for non-KVM

On 26 May 2016 at 15:46, Richard W.M. Jones wrote: > The problem with this is if I'm using TCG fallback mode, how > can I specify the right gic-version? ie: > > -M virt,gic-version=host,accel=kvm:tcg > > Only qemu knows if KVM is going to be enabled. > > The same problem

[Qemu-devel] [RFC PATCH 2/2] add debian-bootstrap.docker target

Together with some changes to the docker script you can now build an arbitrary architecture of Debian using debootstrap. To achieve this I introduce the concept of a HOST_CMD in the docker config file. While copying the file into workspace the HOST_CMD is run in the docker build context. This

[Qemu-devel] [PATCH] hw/arm/virt: Reject gic-version=host for non-KVM

If you try to gic-version=host with TCG on a KVM aarch64 host, qemu segfaults, since host requires KVM APIs. Explicitly reject gic-version=host if KVM is not enabled https://bugzilla.redhat.com/show_bug.cgi?id=1339977 Signed-off-by: Cole Robinson --- hw/arm/virt.c | 6

Re: [Qemu-devel] [PATCH v3 5/5] qcow2: Catch more unaligned write_zero into zero cluster

On 05/26/2016 07:41 AM, Denis V. Lunev wrote: > On 05/26/2016 06:48 AM, Eric Blake wrote: >> is_zero_cluster() and is_zero_cluster_top_locked() are used only >> by qcow2_co_write_zeroes(). The former is too broad (we don't >> care if the sectors we are about to overwrite are non-zero, only >>

Re: [Qemu-devel] [PATCH] hw/arm/virt: Reject gic-version=host for non-KVM

On Thu, May 26, 2016 at 10:31:25AM -0400, Cole Robinson wrote: > If you try to gic-version=host with TCG on a KVM aarch64 host, > qemu segfaults, since host requires KVM APIs. > > Explicitly reject gic-version=host if KVM is not enabled > > https://bugzilla.redhat.com/show_bug.cgi?id=1339977 >

[Qemu-devel] [PATCH v2 13/22] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions

Wire up the MMIO functions exposed by the distributor and the redistributor into MMIO regions exposed by the GICv3 device. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v2 17/22] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers

Implement the registers in the GICv3 CPU interface which generate new SGI interrupts. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 125 + hw/intc/arm_gicv3_redist.c | 40 +++

[Qemu-devel] [PATCH v2 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq()

Implement the code which updates the GIC state when an interrupt input into the GIC is asserted. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3.c| 20 +++- hw/intc/arm_gicv3_dist.c | 21 + hw/intc/arm_gicv3_redist.c |

[Qemu-devel] [PATCH v2 21/22] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes

From: Pavel Fedin This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. FIXME: not-for-upstream Signed-off-by: Pavel Fedin --- linux-headers/asm-arm64/kvm.h | 17 + 1

[Qemu-devel] [PATCH v2 00/22] GICv3 emulation

This series implements emulation of the GICv3 interrupt controller. It is based to some extent on previous patches from Shlomo and Pavel, but the bulk of it has turned out to be new code. (The combination of changing the underlying data structures, adding support for TrustZone and implementing

Re: [Qemu-devel] [PATCH v3 5/5] qcow2: Catch more unaligned write_zero into zero cluster

On 05/26/2016 06:48 AM, Eric Blake wrote: is_zero_cluster() and is_zero_cluster_top_locked() are used only by qcow2_co_write_zeroes(). The former is too broad (we don't care if the sectors we are about to overwrite are non-zero, only that all other sectors in the cluster are zero), so it needs

[Qemu-devel] [PATCH v2 11/22] hw/intc/arm_gicv3: Implement GICv3 distributor registers

From: Shlomo Pongratz Implement the distributor registers of a GICv3. Signed-off-by: Shlomo Pongratz [PMM: significantly overhauled/rewritten: * use the new bitmap data structures * restructure register read/write to handle different

Re: [Qemu-devel] [PULL 25/28] migration: define 'tls-creds' and 'tls-hostname' migration parameters

On 05/26/2016 12:12 AM, Amit Shah wrote: > From: "Daniel P. Berrange" > > Define two new migration parameters to be used with TLS encryption. > The 'tls-creds' parameter provides the ID of an instance of the > 'tls-creds' object type, or rather a subclass such as

[Qemu-devel] [PATCH v2 16/22] hw/intc/arm_gicv3: Implement gicv3_cpuif_update()

Implement the gicv3_cpuif_update() function which deals with correctly asserting IRQ and FIQ based on the current running priority of the CPU, the priority of the highest priority pending interrupt and the CPU's current exception level and security state. Signed-off-by: Peter Maydell

Re: [Qemu-devel] [libvirt] inconsistent handling of "qemu64" CPU model

On 05/26/2016 04:41 AM, Jiri Denemark wrote: The qemu64 CPU model contains svm and thus libvirt will always consider it incompatible with any Intel CPUs (which have vmx instead of svm). On the other hand, QEMU by default ignores features that are missing in the host CPU and has no problem using

Re: [Qemu-devel] [PULL 10/28] migration: add reporting of errors for outgoing migration

On 05/26/2016 12:12 AM, Amit Shah wrote: > From: "Daniel P. Berrange" > > Currently if an application initiates an outgoing migration, > it may or may not, get an error reported back on failure. If > the error occurs synchronously to the 'migrate' command > execution, the

Re: [Qemu-devel] [PATCH] hw/arm/virt: Reject gic-version=host for non-KVM

On Thu, May 26, 2016 at 03:53:54PM +0100, Peter Maydell wrote: > On 26 May 2016 at 15:46, Richard W.M. Jones wrote: > > The problem with this is if I'm using TCG fallback mode, how > > can I specify the right gic-version? ie: > > > > -M virt,gic-version=host,accel=kvm:tcg >

[Qemu-devel] [PATCH v2 10/22] hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending interrupt for each CPU after some part of the GIC state has changed. We avoid unnecessary full recalculation where possible. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3.c| 293

[Qemu-devel] [PATCH v2 15/22] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers

Implement the CPU interface registers for the GICv3; these are CPU system registers, not MMIO registers. This commit implements all the registers which are simple accessors for GIC state, but not those which act as interfaces for acknowledging, dismissing or generating interrupts. (Those will be

[Qemu-devel] [PATCH v2 20/22] target-arm/monitor.c: Advertise emulated GICv3 in capabilities

Now we have an emulated GICv3 we should advertise it via the capabilities in the monitor protocol. Signed-off-by: Peter Maydell --- target-arm/monitor.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target-arm/monitor.c b/target-arm/monitor.c

Re: [Qemu-devel] [PATCH v5 08/14] docker: Add full test

Fam Zheng writes: > This builds all available targets. > > Signed-off-by: Fam Zheng Reviewed-by: Alex Bennée > --- > tests/docker/test-full | 17 + > 1 file changed, 17 insertions(+) > create mode 100755

[Qemu-devel] [PATCH v2 07/22] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure

Move the GICv3 parent_irq and parent_fiq pointers into the GICv3CPUState structure rather than giving them their own array. This will make it easy to assert the IRQ and FIQ lines for a particular CPU interface without having to know or calculate the CPU index for the GICv3CPUState we are working

Re: [Qemu-devel] [PATCH v5 09/14] docker: Add clang test

Fam Zheng writes: > The (currently partially commented out) configure options are suggested > by John Snow . > > Signed-off-by: Fam Zheng Reviewed-by: Alex Bennée > --- > tests/docker/test-clang | 26

[Qemu-devel] [RFC 08/10] cputlb: Query tlb_flush_page_by_mmuidx

Similarly to the previous commit, make tlb_flush_page_by_mmuidx query the flushes when targeting different VCPUs. Signed-off-by: Alvise Rigo --- cputlb.c| 90 ++--- include/exec/exec-all.h | 5 +--

Re: [Qemu-devel] [QEMU RFC PATCH v2 4/6] Migration: migrate QTAILQ

On 26/05/2016 18:43, Jianjun Duan wrote: >>> The user may only care the position of head and entry. But to >>> implement QTAILQ_RAW_***, we need more offset information than that. >>> If we don't query the offsets using something like offset() and store >>> it in a metadata, we have to make the

Re: [Qemu-devel] [PULL V3 00/20] Net patches

On 05/26/2016 09:08 AM, Peter Maydell wrote: > > Apologies for the lack of any backtraces in the output, but > this is almost certainly the result of trying to do le64_to_cpu() > or cpu_to_le64() on a buffer which isn't necessarily aligned > (usually some pointer into guest memory). Use the

[Qemu-devel] [PATCH v2 01/22] migration: Define VMSTATE_UINT64_2DARRAY

Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we already have for other type sizes. Signed-off-by: Peter Maydell --- include/migration/vmstate.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/migration/vmstate.h

Re: [Qemu-devel] [PULL V3 00/20] Net patches

On 26 May 2016 at 16:20, Eric Blake wrote: > On 05/26/2016 09:08 AM, Peter Maydell wrote: >> >> Apologies for the lack of any backtraces in the output, but >> this is almost certainly the result of trying to do le64_to_cpu() >> or cpu_to_le64() on a buffer which isn't

[Qemu-devel] [Bug 1585971] Re: Host system crashes on qemu with DMA remapping

Sorry, i have to cancel this report. The problem seems to be somewhere else. After some reboots the same issue came up again. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1585971 Title: Host

Re: [Qemu-devel] [RFC PATCH 2/3] tcg: Add support for fence generation in x86 backend

Pranith Kumar writes: > Hi Richard, > > Thank you for the helpful comments. > > On Wed, May 25, 2016 at 1:35 PM, Richard Henderson wrote: >> On 05/24/2016 10:18 AM, Pranith Kumar wrote: >>> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h >>>

[Qemu-devel] [RFC 02/10] softmmu_llsc_template.h: Move to multi-threading

Using tcg_exclusive_{lock,unlock}(), make the emulation of LoadLink/StoreConditional thread safe. During an LL access, this lock protects the load access itself, the update of the exclusive history and the update of the VCPU's protected range. In a SC access, the lock protects the store access

[Qemu-devel] [RFC 07/10] cputlb: Query tlb_flush_by_mmuidx

Some architectures need to flush the TLB by MMU index. As per tlb_flush(), also these flushes have to be properly queried to the target VCPU. For the time being, this type of flush is used only in the ARM/aarch64 target architecture and is the result of guest instructions emulation. As a result,

[Qemu-devel] [RFC 03/10] cpus: Introduce async_wait_run_on_cpu()

Introduce a new function that allows the calling VCPU to add a work item to another VCPU (aka target VCPU). This new function differs from async_run_on_cpu() since it makes the calling VCPU waiting for the target VCPU to finish the work item. The mechanism makes use of the halt_cond to wait and in

[Qemu-devel] [RFC 10/10] cpus: Do not sleep if some work item is pending

If a VCPU returns EXCP_HALTED from the guest code execution and in the mean time receives a work item, it will go to sleep without processing the job. Before sleeping, check if any work has been added. Signed-off-by: Alvise Rigo --- cpus.c | 2 +- 1 file changed,

Re: [Qemu-devel] [PULL V3 00/20] Net patches

On 26 May 2016 at 03:16, Jason Wang wrote: > The following changes since commit 287db79df8af8e31f18e262feb5e05103a09e4d4: > > Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into > staging (2016-05-24 13:06:33 +0100) > > are available in the git

[Qemu-devel] [PATCH v2 12/22] hw/intc/arm_gicv3: Implement GICv3 redistributor registers

From: Shlomo Pongratz Implement the redistributor registers of a GICv3. Signed-off-by: Shlomo Pongratz [PMM: significantly overhauled/rewritten: * use the new data structures * restructure register read/write to handle different width

Re: [Qemu-devel] [PATCH 1/4] memory: remove qemu_get_ram_fd, qemu_set_ram_fd, qemu_ram_block_host_ptr

On 26/05/2016 14:22, Marc-André Lureau wrote: > Hi > > On Thu, May 26, 2016 at 10:49 AM, Paolo Bonzini wrote: >> Remove direct uses of ram_addr_t and optimize memory_region_{get,set}_fd >> now that a MemoryRegion knows its RAMBlock directly. >> >> Signed-off-by: Paolo

Re: [Qemu-devel] [PULL 00/28] migration: support for TLS

On 26 May 2016 at 07:11, Amit Shah wrote: > The following changes since commit 287db79df8af8e31f18e262feb5e05103a09e4d4: > > Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into > staging (2016-05-24 13:06:33 +0100) > > are available in the git

[Qemu-devel] [PATCH v2 19/22] target-arm/machine.c: Allow user to request GICv3 emulation

Now we have an emulated GICv3, remove the restriction in gicv3_class_name() so that the user can request a GICv3 with -machine gic-version=3 even when not using KVM. Signed-off-by: Peter Maydell --- target-arm/machine.c | 3 +-- 1 file changed, 1 insertion(+), 2

[Qemu-devel] [PATCH v2 03/22] target-arm: Define new arm_is_el3_or_mon() function

The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Signed-off-by: Peter Maydell

[Qemu-devel] [PATCH v2 02/22] bitops.h: Implement half-shuffle and half-unshuffle ops

A half-shuffle operation takes a word with zeros in the high half: ABCD EFGH IJKL MNOP and spreads the bits out so they are in every other bit of the word: 0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P A half-unshuffle performs the reverse operation. Provide functions in bitops.h

[Qemu-devel] [PATCH v2 04/22] target-arm: Provide hook to tell GICv3 about changes of security state

The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be

Re: [Qemu-devel] [PATCH v5 00/14] tests: Introducing docker tests

Fam Zheng writes: > v5: Use docker run's selinux option "z" on passed volume, drop --privileged. > Allow overriding "TARGET_LIST" in clang-test. > Add Alex's r-b lines in patches 1, 3, 9, 11 and 13. > > This series adds a new "docker" make target family to run tests in

[Qemu-devel] [RFC 09/10] cputlb: Query tlb_flush_page_all

Secure tlb_flush_page_all() by waiting the queried flushes to be actually completed using async_wait_run_on_cpu(); Signed-off-by: Alvise Rigo --- cputlb.c| 15 ++- include/exec/exec-all.h | 4 ++-- target-arm/helper.c | 4 ++-- 3

[Qemu-devel] [RFC 06/10] cputlb: Add tlb_tables_flush_bitmap()

Add a simple helper function to flush the TLB at the indexes specified by a bitmap. The function will be more useful in the following patches, when it will be possible to query tlb_flush_by_mmuidx() to VCPUs. Signed-off-by: Alvise Rigo --- cputlb.c | 30

[Qemu-devel] [PATCH v2 08/22] hw/intc/arm_gicv3: Add vmstate descriptors

From: Pavel Fedin Add state structure descriptors for the GICv3 state. We mark the KVM GICv3 device as having a migration blocker until the code to save and restore the state in the kernel is implemented. Signed-off-by: Pavel Fedin [PMM: Adjust to

[Qemu-devel] [PATCH v2 09/22] hw/intc/arm_gicv3: ARM GICv3 device framework

From: Shlomo Pongratz This patch includes the device class itself, some ID register value functions which will be needed by both distributor and redistributor, and some skeleton functions for handling interrupts coming in and going out, which will be filled in in a

[Qemu-devel] [PATCH v2 22/22] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Pavel Fedin This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin [PMM: * use decimal, not 0bnnn * fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1 * completely rearranged the get and put

[Qemu-devel] [PATCH v2 05/22] target-arm: Add mp-affinity property for ARM CPU class

From: Pavel Fedin This allows to override default affinity IDs on a per-machine basis, and possibility to retrieve IDs will be used by vGICv3 live migration code. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell ---

[Qemu-devel] [PATCH v2 18/22] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers

Add the CPU interface registers which deal with acknowledging and dismissing interrupts. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 437 ++ hw/intc/gicv3_internal.h | 5 + trace-events | 7

[Qemu-devel] [Bug 1585971] [NEW] Host system crashes on qemu with DMA remapping

Public bug reported: Hy, the host system crashes completely, when i try to pass an physical device without boot option intel_iommu=on set. In older kernel versions you didn't have to pass that option. I wonder if this can be easily checked by asking iommu state, avoiding a crash of the complete

Re: [Qemu-devel] [PATCH v5 09/14] docker: Add clang test

Fam Zheng writes: > The (currently partially commented out) configure options are suggested > by John Snow . > > Signed-off-by: Fam Zheng Reviewed-by: Alex Bennée > --- > tests/docker/test-clang | 26

Re: [Qemu-devel] qemu-arm-static, multiprocess, atomic

On 26/05/2016 14:53, Sergey Fedorov wrote: >>> I'm afraid even our recent efforts in >>> multi-threaded TCG won't change the situation. The problem is that it >>> would require to translate somehow ARM's exclusive access monitor to x86 >>> model. >>> >> The cmpxchg-based variant would work. It

[Qemu-devel] [PATCH v2 06/22] hw/intc/arm_gicv3: Add state information

From: Pavel Fedin Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin [PMM:

[Qemu-devel] [RFC 00/10] MTTCG: Slow-path for atomic insns

Hi, This series ports the latest iteration of the LL/SC work on top of the latest MTTCG reference branch posted recently by Alex. These patches apply on top of the following series: - [RFC v1 00/12] Enable MTTCG for 32 bit arm on x86

[Qemu-devel] [RFC 01/10] exec: Introduce tcg_exclusive_{lock, unlock}()

Add tcg_exclusive_{lock,unlock}() functions that will be used for making the emulation of LL and SC instructions thread safe. Signed-off-by: Alvise Rigo --- cpus.c| 2 ++ exec.c| 18 ++ include/qom/cpu.h | 5 + 3 files

[Qemu-devel] [RFC 04/10] cputlb: Introduce tlb_flush_other()

In some cases (like in softmmu_llsc_template.h) we know for certain that we need to flush other VCPUs' TLB. tlb_flush_other() serves this purpose, allowing the VCPU @cpu to query a global flush to @other. In addition, use it also in softmmu_llsc_template.h and tlb_flush() if possible.

[Qemu-devel] [RFC 05/10] target-arm: End TB after ldrex instruction

A VCPU executing a ldrex instruction might query flushes to other VCPUs: in this cases, the calling VCPU uses cpu_exit to exit from the cpu loop and wait the other VCPUs to perform the flush. In order to exit from the cpu loop as soon as possible, interrupt the TB after the ldrex instruction.

Re: [Qemu-devel] [QEMU RFC PATCH v2 4/6] Migration: migrate QTAILQ

On 05/26/2016 12:11 AM, Paolo Bonzini wrote: > > > On 25/05/2016 22:17, Jianjun Duan wrote: >> >> >> On 05/25/2016 12:22 PM, Paolo Bonzini wrote: 1 QTAILQ should only be accessed using the interfaces defined in queue.h. Its structs should not be directly used. So I created

[Qemu-devel] [PULL 06/11] vfio/pci: Intel graphics legacy mode assignment

Enable quirks to support SandyBridge and newer IGD devices as primary VM graphics. This requires new vfio-pci device specific regions added in kernel v4.6 to expose the IGD OpRegion, the shadow ROM, and config space access to the PCI host bridge and LPC/ISA bridge. VM firmware support, SeaBIOS

[Qemu-devel] [PULL 07/11] vfio/pci: Add a separate option for IGD OpRegion support

The IGD OpRegion is enabled automatically when running in legacy mode, but it can sometimes be useful in universal passthrough mode as well. Without an OpRegion, output spigots don't work, and even though Intel doesn't officially support physical outputs in UPT mode, it's a useful feature. Note

[Qemu-devel] [PULL 09/11] vfio: Fix 128 bit handling when deleting region

From: Alexey Kardashevskiy 7532d3cbf "vfio: Fix 128 bit handling" added support for 64bit IOMMU memory regions when those are added to VFIO address space; however removing code cannot cope with these as int128_get64() will fail on 1<<64. This copies 128bit handling from

Re: [Qemu-devel] use timer for adding latency to each block I/O

> On May 16, 2016, at 11:33 AM, Stefan Hajnoczi wrote: > > The way it's done in the "null" block driver is: > > static coroutine_fn int null_co_common(BlockDriverState *bs) > { >BDRVNullState *s = bs->opaque; > >if (s->latency_ns) { >

Re: [Qemu-devel] [PULL 00/11] VFIO updates 2016-05-26

On 26 May 2016 at 19:00, Alex Williamson wrote: > The following changes since commit 2c56d06bafd8933d2a9c6e0aeb5d45f7c1fb5616: > > Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging > (2016-05-26 14:29:30 +0100) > > are available in the git

[Qemu-devel] [PULL 02/11] vfio: Create device specific region info helper

Given a device specific region type and sub-type, find it. Also cleanup return point on error in vfio_get_region_info() so that we always return 0 with a valid pointer or -errno and NULL. Signed-off-by: Alex Williamson Reviewed-by: Gerd Hoffmann

[Qemu-devel] [PULL 01/11] vfio: Enable sparse mmap capability

The sparse mmap capability in a vfio region info allows vfio to tell us which sub-areas of a region may be mmap'd. Thus rather than assuming a single mmap covers the entire region and later frobbing it ourselves for things like the PCI MSI-X vector table, we can read that directly from vfio.

[Qemu-devel] [PULL 05/11] vfio/pci: Setup BAR quirks after capabilities probing

Capability probing modifies wmask, which quirks may be interested in changing themselves. Apply our BAR quirks after the capability scan to make this possible. Signed-off-by: Alex Williamson Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann

[Qemu-devel] [PULL 00/11] VFIO updates 2016-05-26

The following changes since commit 2c56d06bafd8933d2a9c6e0aeb5d45f7c1fb5616: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-05-26 14:29:30 +0100) are available in the git repository at: git://github.com/awilliam/qemu-vfio.git tags/vfio-update-20160526.1

[Qemu-devel] [PULL 03/11] vfio/pci: Fix return of vfio_populate_vga()

This function returns success if either we setup the VGA region or the host vfio doesn't return enough regions to support the VGA index. This latter case doesn't make any sense. If we're asked to populate VGA, fail if it doesn't exist and let the caller decide if that's important. Signed-off-by:

[Qemu-devel] [PULL 11/11] vfio: Check that IOMMU MR translates to system address space

From: Alexey Kardashevskiy At the moment IOMMU MR only translate to the system memory. However if some new code changes this, we will need clear indication why it is not working so here is the check. Signed-off-by: Alexey Kardashevskiy Reviewed-by: David Gibson

[Qemu-devel] [PULL 04/11] vfio/pci: Consolidate VGA setup

Combine VGA discovery and registration. Quirks can have dependencies on BARs, so the quirks push out until after we've scanned the BARs. Signed-off-by: Alex Williamson Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann ---

[Qemu-devel] [PULL 08/11] vfio/pci: Add IGD documentation

Document the usage modes, host primary graphics considerations, usage, and fw_cfg ABI required for IGD assignment with vfio. Signed-off-by: Alex Williamson Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann ---

[Qemu-devel] [PULL 10/11] memory: Fix IOMMU replay base address

From: Alexey Kardashevskiy Since a788f227 "memory: Allow replay of IOMMU mapping notifications" when new VFIO listener is added, all existing IOMMU mappings are replayed. However there is a problem that the base address of an IOMMU memory region (IOMMU MR) is ignored which is not

[Qemu-devel] [PULL 20/28] migration: delete QEMUSizedBuffer struct

From: "Daniel P. Berrange" Now that we don't have have a buffer based QemuFile implementation, the QEMUSizedBuffer code is also unused and can be deleted. A simpler buffer class also exists in util/buffer.c which other code can used as needed. Reviewed-by: Dr. David Alan

[Qemu-devel] [PULL 08/28] migration: introduce a new QEMUFile impl based on QIOChannel

From: "Daniel P. Berrange" Introduce a new QEMUFile implementation that is based on the QIOChannel objects. This impl is different from existing impls in that there is no file descriptor that can be made available, as some channels may be based on higher level protocols such

[Qemu-devel] [PULL 17/28] migration: convert RDMA to use QIOChannel interface

From: "Daniel P. Berrange" This converts the RDMA code to provide a subclass of QIOChannel that uses RDMA for the data transport. This implementation of RDMA does not correctly handle non-blocking mode. Reads might block if there was not already some pending data and writes

[Qemu-devel] [PULL 23/28] migration: move definition of struct QEMUFile back into qemu-file.c

From: "Daniel P. Berrange" Now that the memory buffer based QEMUFile impl is gone, there is no need for any backend to be accessing internals of the QEMUFile struct, so it can be moved back into qemu-file.c Reviewed-by: Dr. David Alan Gilbert

[Qemu-devel] [PULL 25/28] migration: define 'tls-creds' and 'tls-hostname' migration parameters

From: "Daniel P. Berrange" Define two new migration parameters to be used with TLS encryption. The 'tls-creds' parameter provides the ID of an instance of the 'tls-creds' object type, or rather a subclass such as 'tls-creds-x509'. Providing these credentials will enable use

[Qemu-devel] [PATCH 2/2] scsi-generic: Merge block max xfer len in INQUIRY response

The rationale is similar to the above mode sense response interception: this is practically the only channel to communicate restraints from elsewhere such as host and block driver. The scsi bus we attach onto can have a larger max xfer len than what is accepted by the host file system (guarding

[Qemu-devel] [PATCH 4/4] exec: hide mr->ram_addr from qemu_get_ram_ptr users

Let users of qemu_get_ram_ptr and qemu_ram_ptr_length pass in an address that is relative to the MemoryRegion. This basically means what address_space_translate returns. Because the semantics of the second parameter change, rename the function to qemu_map_ram_ptr. Signed-off-by: Paolo Bonzini

[Qemu-devel] [PULL 05/28] migration: split migration hooks out of QEMUFileOps

From: "Daniel P. Berrange" The QEMUFileOps struct contains the I/O subsystem callbacks and the migration stage hooks. Split the hooks out into a separate QEMUFileHooks struct to make it easier to refactor the I/O side of QEMUFile without affecting the hooks. Reviewed-by:

[Qemu-devel] [PULL 14/28] migration: convert tcp socket protocol to use QIOChannel

From: "Daniel P. Berrange" Drop the current TCP socket migration driver and extend the new generic socket driver to cope with the TCP address format Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Daniel P. Berrange Message-Id:

[Qemu-devel] [PULL 26/28] migration: add support for encrypting data with TLS

From: "Daniel P. Berrange" This extends the migration_set_incoming_channel and migration_set_outgoing_channel methods so that they will automatically wrap the QIOChannel in a QIOChannelTLS instance if TLS credentials are configured in the migration parameters. This allows

[Qemu-devel] [PULL 21/28] migration: delete QEMUFile sockets implementation

From: "Daniel P. Berrange" Now that the tcp, unix and fd migration backends have converted to use the QIOChannel based QEMUFile, there is no user remaining for the sockets based QEMUFile impl and it can be deleted. Reviewed-by: Dr. David Alan Gilbert

Re: [Qemu-devel] [Qemu-ppc] [PATCH] MAINTAINERS: Add David Gibson as ppc maintainer

On 26/05/16 07:16, David Gibson wrote: > I've been de facto co-maintainer of all ppc target related code for some > time. Alex Graf isworking on other things and doesn't have a whole lot of > time for qemu ppc maintainership. So, update the MAINTAINERS file to > reflect this. > >

Re: [Qemu-devel] [for-2.7 PATCH v3 00/15] Core based CPU hotplug for PowerPC sPAPR

On Thu, May 12, 2016 at 09:18:10AM +0530, Bharata B Rao wrote: > Hi, > > This is v3 of "Core based CPU hotplug for PowerPC sPAPR". The hotplug > semantics looks like this: > > (qemu) device_add POWER8E-spapr-cpu-core,id=core2,core=16[,threads=4] > (qemu) device_add

Re: [Qemu-devel] [PATCH V2] block/io: optimize bdrv_co_pwritev for small requests

On Thu, 05/26 14:50, Fam Zheng wrote: > On Tue, 05/24 16:30, Peter Lieven wrote: > > in a read-modify-write cycle a small request might cause > > head and tail to fall into the same aligned block. Currently > > QEMU reads the same block twice in this case which is > > not necessary. > > > >

[Qemu-devel] Help me with QEMU

Hello,respected developers of Qemu. I am new to Qemu,and I have some questions below.Any help would be highly appreciated! question 1: How can I add a kind of new device support in Qemu and What is the steps to do so?(For example,if Qemu can not virtualize the RAM ,what should I do to make

Re: [Qemu-devel] Help me with QEMU

> How can I add a kind of new device support in Qemu and What is the steps to do so? https://github.com/rafilia/qemu_example_virtual_pcidev -- Dongli Zhang (张东立) finallyjustice.github.io

[Qemu-devel] [PATCH 2/3] linux-headers: update to Linux 4.6

Signed-off-by: Greg Kurz --- include/standard-headers/linux/pci_regs.h | 20 +++- include/standard-headers/linux/virtio_config.h |2 ++ linux-headers/asm-arm/unistd.h |2 ++ linux-headers/asm-arm64/unistd.h |

[Qemu-devel] [PATCH 0/3] PPC/KVM support higher vCPU ids

Now that KVM_CAP_MAX_VCPU_ID is in Linux 4.6, we can use it to support topologies that generate vCPU ids >= KVM_MAX_VCPUS. This is especially useful for PPC targets when the guest has fewer threads per core than the host. The first patch was already posted and accepted by David last month, but

[Qemu-devel] [PULL 10/28] migration: add reporting of errors for outgoing migration

From: "Daniel P. Berrange" Currently if an application initiates an outgoing migration, it may or may not, get an error reported back on failure. If the error occurs synchronously to the 'migrate' command execution, the client app will see the error message. This is the case

[Qemu-devel] [PULL 13/28] migration: rename unix.c to socket.c

From: "Daniel P. Berrange" The unix.c file will be nearly the same as the tcp.c file, only differing in the initial SocketAddress creation code. Rename unix.c to socket.c and refactor it a little to prepare for merging the TCP code. Reviewed-by: Dr. David Alan Gilbert

[Qemu-devel] [PULL 15/28] migration: convert fd socket protocol to use QIOChannel

From: "Daniel P. Berrange" Convert the fd socket migration protocol driver to use QIOChannel and QEMUFileChannel, instead of plain sockets APIs. It can be unconditionally built because the QIOChannel APIs it uses will take care to report suitable error messages if needed.

[Qemu-devel] [PULL 07/28] migration: force QEMUFile to blocking mode for outgoing migration

From: "Daniel P. Berrange" Instead of relying on the default QEMUFile I/O blocking flag state, explicitly turn on blocking I/O for outgoing migration since it takes place in a background thread. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Daniel

[Qemu-devel] [PULL 19/28] migration: delete QEMUFile buffer implementation

From: "Daniel P. Berrange" The qemu_bufopen() method is no longer used, so the memory buffer based QEMUFile backend can be deleted entirely. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Daniel P. Berrange Message-Id:

[Qemu-devel] [PULL 27/28] migration: remove support for non-iovec based write handlers

From: "Daniel P. Berrange" All the remaining QEMUFile implementations provide an iovec based write handler, so the put_buffer callback can be removed to simplify the code. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Daniel P. Berrange

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