Re: [Qemu-devel] [PATCH 3/4] acpi: provide _PXM method for CPU devices if QEMU is started numa enabled

On Thu, 30 Jun 2016 20:47:33 +0300 "Michael S. Tsirkin" wrote: Thanks for review, I'll fix up patch according to your comments and post v3 shortly > On Thu, Jun 30, 2016 at 02:23:06PM +0200, Igor Mammedov wrote: > > fixes long standing issue where Linux kernel would assing >

Re: [Qemu-devel] [PULL 0/6] ipxe: update submodule from 4e03af8ec to 041863191

On Do, 2016-06-30 at 17:37 +0100, Peter Maydell wrote: > On 30 June 2016 at 17:21, Gerd Hoffmann wrote: > > Hi, > > > >> Hi. I'm afraid this fails 'make check': > >> TEST: tests/vmxnet3-test... (pid=19181) > >> qemu-system-i386: -device vmxnet3: failed to find romfile

Re: [Qemu-devel] Bug in virtio_net_load

On Thu, 30 Jun 2016 20:23:08 +0300 "Michael S. Tsirkin" wrote: > I'm not sure what was I thinking when I applied this: > it changes load without changing save - how can this work? The ordering implications are easy to miss :( > I am inclined to revert

Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property

On 1 July 2016 at 07:11, Cédric Le Goater wrote: > On 06/30/2016 08:24 PM, Peter Maydell wrote: >> On 30 June 2016 at 16:50, Cédric Le Goater wrote: >>> These strap registers are complex enough, let's not mix them. >>> >>> Signed-off-by: Cédric Le Goater

Re: [Qemu-devel] [PATCH v2] spec/qcow2: bitmaps: zero bitmap table offset

Am 30.06.2016 um 19:23 hat Denis V. Lunev geschrieben: > On 06/30/2016 07:40 PM, John Snow wrote: > > > >On 06/30/2016 05:12 AM, Denis V. Lunev wrote: > >>On 06/30/2016 10:34 AM, Vladimir Sementsov-Ogievskiy wrote: > >>>After loading bitmap from image and setting IN_USE flag in it's header, >

Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property

On 07/01/2016 10:02 AM, Peter Maydell wrote: > On 1 July 2016 at 07:11, Cédric Le Goater wrote: >> On 06/30/2016 08:24 PM, Peter Maydell wrote: >>> On 30 June 2016 at 16:50, Cédric Le Goater wrote: These strap registers are complex enough, let's not mix them.

[Qemu-devel] [Bug 1297218] Re: guest hangs after live migration due to tsc jump

I can reasonably assume that this solved my problem. I've live migrated 41 VM's 5 times between 2 hypervisors without the 100% cpu problem appearing. My production servers run 2.0.0+dfsg-2ubuntu1.22, and still observe the same problem. Attached is the patch that I created with quilt in

Re: [Qemu-devel] [PATCH] virtio: revert host notifiers to old semantics

Hi On Thu, Jun 30, 2016 at 5:31 PM, Cornelia Huck wrote: > The host notifier rework tried both to unify host notifiers across > transports and plug a possible hole during host notifier > re-assignment. Unfortunately, this meant a change in semantics that > breaks vhost

Re: [Qemu-devel] [RFC 6/8] linux-user: Support CPU work queue

On 30/06/16 13:35, Sergey Fedorov wrote: > On 30/06/16 13:32, Alex Bennée wrote: >> Sergey Fedorov writes: >> >>> On 29/06/16 19:17, Alex Bennée wrote: So I think there is a deadlock we can get with the async work: (gdb) thread apply all bt Thread 11

Re: [Qemu-devel] [RFC 6/8] linux-user: Support CPU work queue

On 01/07/16 11:56, Sergey Fedorov wrote: > On 30/06/16 13:35, Sergey Fedorov wrote: >> On 30/06/16 13:32, Alex Bennée wrote: >>> Sergey Fedorov writes: >>> On 29/06/16 19:17, Alex Bennée wrote: > So I think there is a deadlock we can get with the async work: >

[Qemu-devel] [Bug 1594239] Re: After adding more scsi disks for Aarch64 virtual machine, start the VM and got Qemu Error

Hi Tom, Yeh it's just vmstate_register_with_alias_id printing vmsd->name at entry, and then after the char *id = printing that as well (that's what I labelled as the dev/id case). Then just before the assert I was printing the se->compat and se->instance_id values. I noticed this bug

Re: [Qemu-devel] [PATCH v2] spec/qcow2: bitmaps: zero bitmap table offset

On 01.07.2016 11:12, Kevin Wolf wrote: Am 30.06.2016 um 19:23 hat Denis V. Lunev geschrieben: On 06/30/2016 07:40 PM, John Snow wrote: On 06/30/2016 05:12 AM, Denis V. Lunev wrote: On 06/30/2016 10:34 AM, Vladimir Sementsov-Ogievskiy wrote: After loading bitmap from image and setting IN_USE

Re: [Qemu-devel] [PATCH] balloon: Fix failure of updating guest memory status

> > +if (s->stats_vq_elem == NULL) { > > +virtqueue_push(s->svq, , 0); > > +virtio_notify(vdev, s->svq); > > +return; > > +} > > virtqueue_push(s->svq, s->stats_vq_elem, s->stats_vq_offset); > > virtio_notify(vdev, s->svq); > >

[Qemu-devel] [PATCH 1/2] ipxe: add new roms to BLOBS

Signed-off-by: Gerd Hoffmann --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 7087fc2..5ea13bc 100644 --- a/Makefile +++ b/Makefile @@ -416,6 +416,7 @@ pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \ pxe-pcnet.rom pxe-rtl8139.rom

[Qemu-devel] [PATCH 2/2] build: add pc-bios to config-host.mak deps

... so configure re-runs on pc-bios updates such as new pxe roms. Needed because configure symlinks the prebuilt roms from src into build tree. Signed-off-by: Gerd Hoffmann --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile

[Qemu-devel] [PATCH v2 1/2] piix: Set I440FXState member pci_info.w32 in one place

Range pci_info.w32 records the location of the PCI hole. It's initialized to empty when QOM zeroes I440FXState. That's a fine value for a still unknown PCI hole. i440fx_init() sets pci_info.w32.begin = below_4g_mem_size. Changes the PCI hole from empty to [below_4g_mem_size, UINT64_MAX].

[Qemu-devel] [PATCH v3 0/4] range: Make it simpler & safer

Looks ready to me. My current qapi-next is based on it, so I'd appreciate merge or further review. Thanks! Prerequisites: * [PATCH v2 0/2] Clean up around the PCI holes v2: * Trivially rebased v1 RFC: * PATCH 2+3 squashed * PATCH 4 (now 3) clarify range_compare() doesn't work for empty

[Qemu-devel] [PATCH v3 4/4] log: Permit -dfilter 0..0xffffffffffffffff

Works fine since the previous commit fixed the underlying range data type. Of course it filters out nothing, but so does 0..1,2..0x, and we don't bother rejecting that either. Signed-off-by: Markus Armbruster Reviewed-by: Eric Blake ---

[Qemu-devel] [PATCH v3 1/4] log: Clean up misuse of Range for -dfilter

Range encodes an integer interval [a,b] as { begin = a, end = b + 1 }, where a \in [0,2^64-1] and b \in [1,2^64]. Thus, zero end is to be interpreted as 2^64. The implementation of -dfilter (commit 3514552) uses Range differently: it encodes [a,b] as { begin = a, end = b }. The code works, but

[Qemu-devel] [PATCH v3 2/5] tests: DO NOT APPLY: add APIC.cphp and DSDT.cphp blobs

Signed-off-by: Igor Mammedov --- tests/acpi-test-data/pc/APIC.cphp | Bin 0 -> 160 bytes tests/acpi-test-data/pc/DSDT.cphp | Bin 0 -> 6435 bytes tests/acpi-test-data/q35/APIC.cphp | Bin 0 -> 160 bytes tests/acpi-test-data/q35/DSDT.cphp | Bin 0 -> 9197 bytes 4 files

Re: [Qemu-devel] [PATCH v3 3/5] numa: reduce code duplication by adding helper numa_get_node_for_cpu()

On Fri, Jul 01, 2016 at 01:50:24PM +0200, Igor Mammedov wrote: > Replace repeated pattern > > for (i = 0; i < nb_numa_nodes; i++) { > if (test_bit(idx, numa_info[i].node_cpu)) { >... >break; > > with a helper function to lookup numa node index for cpu. > >

Re: [Qemu-devel] [PULL v2 0/7] QAPI patches 2016-06-30

On 30 June 2016 at 14:42, Markus Armbruster wrote: > The following changes since commit 297e8005f88d4360480eaa2c07220fa8853f0448: > > MAINTAINERS: Remove Blue Swirl leftovers (2016-06-30 13:34:49 +0100) > > are available in the git repository at: > >

[Qemu-devel] [RFC PATCH 2/2] serial console, input

Signed-off-by: Gerd Hoffmann --- src/clock.c | 1 + src/serial.c | 255 +++ src/util.h | 1 + 3 files changed, 257 insertions(+) diff --git a/src/clock.c b/src/clock.c index e83e0f3..e44e112 100644 ---

[Qemu-devel] [PATCH v2 2/2] pc: Eliminate PcPciInfo

PcPciInfo has two (ill-named) members: Range w32 is the PCI hole, and w64 is the PCI64 hole. Three users: * I440FXState and MCHPCIState have a member PcPciInfo pci_info, but only pci_info.w32 is actually used. This is confusing. Replace by Range pci_hole. * acpi_build() uses auto

[Qemu-devel] [PATCH v2 0/2] Clean up around the PCI holes

Two weeks on list, two R-bys, time to merge. Michael, the orthodox route would be through your tree, but I can do a pull request myself if you're busy. v2: Trivially rebased Markus Armbruster (2): piix: Set I440FXState member pci_info.w32 in one place pc: Eliminate PcPciInfo

Re: [Qemu-devel] [PATCH] hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT

On Thu, Jun 30, 2016 at 03:09:53PM +0100, Peter Maydell wrote: > On 28 June 2016 at 18:14, Ard Biesheuvel wrote: > > Since QEMU performs cacheable accesses to guest memory when doing DMA > > as part of the implementation of emulated PCI devices, guest drivers > > should

[Qemu-devel] [PATCH v3 0/5] fix numa node mapping for hotplugged CPUs

Changelog: v1->v3: - fix commit message for 4/5 - add numa_get_node_for_cpu() helper - add comment in code explaining why _PXM is being added Series adds acpi tables tests for CPU hotplug and makes hotplugged CPUs assigned to correct numa nodes for Linux guests + extends CPU hotplug test

Re: [Qemu-devel] [PATCH v5 00/15] Add clone visitor

Markus Armbruster writes: > Eric Blake writes: > >> [First half of v4 00/28 Add qapi-to-JSON and clone visitors: >> https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg03220.html] >> >> No hard prerequisites; applies to master >> >> Soft prerequisites

[Qemu-devel] [PATCH v3 3/5] numa: reduce code duplication by adding helper numa_get_node_for_cpu()

Replace repeated pattern for (i = 0; i < nb_numa_nodes; i++) { if (test_bit(idx, numa_info[i].node_cpu)) { ... break; with a helper function to lookup numa node index for cpu. Suggested-by: Michael S. Tsirkin Signed-off-by: Igor Mammedov

Re: [Qemu-devel] [PULL 0/5] VFIO updates 2016-06-30

On 30 June 2016 at 20:52, Alex Williamson wrote: > The following changes since commit 8a0b4de048e20215415b24c7b42514c27b9d6ef3: > > pcspk: fix KVM (2016-06-30 19:00:02 +0100) > > are available in the git repository at: > > git://github.com/awilliam/qemu-vfio.git

[Qemu-devel] [PATCH for-2.7] aux: Rename aux.[ch] to auxbus.[ch] for the benefit of Windows

On Windows 'aux.*' is a reserved name and cannot be used for filenames; see https://msdn.microsoft.com/en-gb/library/windows/desktop/aa365247(v=vs.85).aspx This prevents cloning the QEMU git repo on Windows: C:\Java\sources\kvm> git clone https://github.com/qemu/qemu.git Cloning into

[Qemu-devel] [PATCH v3 3/4] range: Replace internal representation of Range

Range represents a range as follows. Member @start is the inclusive lower bound, member @end is the exclusive upper bound. Zero @end is special: if @start is also zero, the range is empty, else @end is to be interpreted as 2^64. No other empty ranges may occur. The range [0,2^64-1] cannot be

[Qemu-devel] [PATCH v3 5/5] tests: acpi: extend cphp testcase with numa check

so it would be possible to verify _PXM generation in DSDT and SRAT tables. Signed-off-by: Igor Mammedov Reviewed-by: Marcel Apfelbaum --- NOTE to maintainer: SRAT table is included in patch as it doesn't have any chance for conflicts compared to often

[Qemu-devel] [PATCH v3 2/4] range: Eliminate direct Range member access

Users of struct Range mess liberally with its members, which makes refactoring hard. Create a set of methods, and convert all users to call them instead of accessing members. The methods have carefully worded contracts, and use assertions to check them. Signed-off-by: Markus Armbruster

[Qemu-devel] [PATCH v3 1/5] tests: acpi: add CPU hotplug testcase

Test with: -smp 2,cores=3,sockets=2,maxcpus=6 to capture sparse APIC ID values that default AMD CPU has in above configuration. Signed-off-by: Igor Mammedov Reviewed-by: Marcel Apfelbaum --- NOTE to maintainer: following table blobs should be added

[Qemu-devel] [PATCH v3 4/5] acpi: provide _PXM method for CPU devices if QEMU is started numa enabled

Workaround for long standing issue where Linux kernel assigns hotplugged CPU to 1st numa node as it discards proximity for possible CPUs from SRAT after it's parsed. _PXM method allows linux query proximity directly from hotplugged CPU object, which allows Linux to assing CPU to the correct numa

Re: [Qemu-devel] [SeaBIOS] [PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL

On Mi, 2016-06-22 at 14:53 +0800, Haozhong Zhang wrote: > OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL > for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file > "etc/msr_feature_control" to advise bits that should be set in > MSR_IA32_FEATURE_CONTROL. If

Re: [Qemu-devel] [PULL 21/32] char: clean up remaining chardevs when leaving

On Tue, Jun 28, 2016 at 07:33:51PM +0200, Paolo Bonzini wrote: > From: Marc-André Lureau > > This helps to remove various chardev resources leaks when leaving qemu. > > Signed-off-by: Marc-André Lureau > Message-Id:

[Qemu-devel] [PATCH 1/2] vhost-user: Attempt to fix a race with set_mem_table.

From: Prerna Saxena The set_mem_table command currently does not seek a reply. Hence, there is no easy way for a remote application to notify to QEMU when it finished setting up memory, or if there were errors doing the so. As an example: (1) Qemu sends a

[Qemu-devel] [PATCH 2/2] vhost-user : Introduce a new protocol feature REPLY_ACK.

From: Prerna Saxena This introduces the VHOST_USER_PROTOCOL_F_REPLY_ACK. If negotiated, client applications should send a u64 payload in response to any message that contains the "need_response" bit set on the message flags. Setting the payload to "zero" indicates the

[Qemu-devel] [PATCH v2 0/2]vhost-user: Extend protocol to seek response for any command.

From: Prerna Saxena The current vhost-user protocol requires the client to send responses to only a few commands. For the remaining commands, it is impossible for QEMU to know the status of the requested operation -- ie, did it succeed? If so, by what time? This is

Re: [Qemu-devel] [PATCH] linux-user: Fix compilation when F_SETPIPE_SZ isn't defined

On 30 June 2016 at 18:51, Laurent Vivier wrote: > > > Le 30/06/2016 à 18:33, Peter Maydell a écrit : >> Older kernels don't have F_SETPIPE_SZ and F_GETPIPE_SZ (in >> particular RHEL6's system headers don't define these). Add >> ifdefs so that we can gracefully fall back to not

[Qemu-devel] [RFC PATCH 1/2] serial console, output

Signed-off-by: Gerd Hoffmann --- src/misc.c | 2 + src/optionroms.c | 4 +- src/serial.c | 340 +++ src/util.h | 2 + 4 files changed, 347 insertions(+), 1 deletion(-) diff --git a/src/misc.c

[Qemu-devel] [RFC PATCH 0/2] seabios: add serial console support

Hi, Ok folks, finally took the time to put serial console support into seabios natively, without requiring sgabios. For now this will use the first serial port in case no vgabios was found, i.e. use something along the lines of "qemu -vga none -serial stdio" to check it out. Design goal is to

Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property

On 06/30/2016 08:24 PM, Peter Maydell wrote: > On 30 June 2016 at 16:50, Cédric Le Goater wrote: >> These strap registers are complex enough, let's not mix them. >> >> Signed-off-by: Cédric Le Goater > > Was there a cover letter for this patchset? I can't find > it

[Qemu-devel] [PULL 11/23] spapr: Restore support for older PowerPC CPU cores

From: Bharata B Rao Introduction of core based CPU hotplug for PowerPC sPAPR didn't add support for 970 and POWER5+ based core types. Add support for the same. Signed-off-by: Bharata B Rao Signed-off-by: David Gibson

[Qemu-devel] [PULL 07/23] ppc: LPCR is a HV resource

From: Benjamin Herrenschmidt Don't allow access in guest mode Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- target-ppc/translate_init.c | 9

[Qemu-devel] [PULL 10/23] spapr: fix write-past-end-of-array error in cpu core device init code

From: Greg Kurz This fixes a potential QEMU crash introduced by commit 3b542549661. Signed-off-by: Greg Kurz Signed-off-by: David Gibson --- hw/ppc/spapr_cpu_core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff

[Qemu-devel] [PULL 02/23] ppc: Update LPCR definitions

From: Benjamin Herrenschmidt Includes all the bits up to ISA 2.07 Signed-off-by: Benjamin Herrenschmidt [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson

[Qemu-devel] [PULL 08/23] ppc: Print HSRR0/HSRR1 in "info registers"

From: Benjamin Herrenschmidt They are generally useful when debugging HV mode stuff Signed-off-by: Benjamin Herrenschmidt [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson

[Qemu-devel] [PULL 04/23] ppc: Fix conditions for delivering external interrupts to a guest

From: Benjamin Herrenschmidt External interrupts can bypass the MSR_EE test if they occur in guest mode and LPES0 is clear. In that case they are directed to the hypervisor Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Cédric Le Goater

[Qemu-devel] [PULL 16/23] ppc/xics: Implement H_IPOLL using an accessor

From: Benjamin Herrenschmidt None of the other presenter functions directly mucks with the internal state, so don't do it there either. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 13/23] ppc: Fix 64K pages support in full emulation

From: Benjamin Herrenschmidt We were always advertising only 4K & 16M. Additionally the code wasn't properly matching the page size with the PTE content, which meant we could potentially hit an incorrect PTE if the guest used multiple sizes. Finally, honor the CPU

[Qemu-devel] [PULL 18/23] target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso

From: Aaron Larson Call gen_pause for all "or rx,rx,rx" encodings other nop. This provides a reasonable implementation for yield, and a better approximation for mdoio, mdoom, and miso. The choice to pause for all encodings !=0 leverages the PowerISA admonition that the

[Qemu-devel] [PULL 06/23] ppc: Initial HDEC support

From: Benjamin Herrenschmidt The current behaviour isn't completely right, as for the DEC, we don't properly re-arm when wrapping around, but I will fix this in a separate patch. Signed-off-by: Benjamin Herrenschmidt [clg: fixed checkpatch.pl

Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property

On 07/01/2016 08:11 AM, Cédric Le Goater wrote: > On 06/30/2016 08:24 PM, Peter Maydell wrote: >> On 30 June 2016 at 16:50, Cédric Le Goater wrote: >>> These strap registers are complex enough, let's not mix them. >>> >>> Signed-off-by: Cédric Le Goater >> >> Was

[Qemu-devel] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set

From: Benjamin Herrenschmidt The architecture specifies that any instruction that sets MSR:PR will also set MSR:EE, IR and DR. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson

[Qemu-devel] [PULL 09/23] hw/ppc/spapr: Add some missing hcall function set strings

From: Thomas Huth Add "hcall-sprg0" (for H_SET_SPRG0), "hcall-copy" (for H_PAGE_INIT) and "hcall-debug" (for H_LOGICAL_CI_LOAD/STORE) to the property "ibm,hypertas-functions" to indicate that we support these hypercalls. Signed-off-by: Thomas Huth

[Qemu-devel] [PULL 21/23] spapr: do proper error propagation in spapr_cpu_core_realize_child()

From: Greg Kurz This patch changes spapr_cpu_core_realize_child() to have a local error pointer and use error_propagate() as it is supposed to be done. Signed-off-by: Greg Kurz Reviewed-by: Bharata B Rao Signed-off-by: David Gibson

[Qemu-devel] [PULL 22/23] spapr: drop duplicate variable in spapr_core_release()

From: Greg Kurz Signed-off-by: Greg Kurz Reviewed-by: Bharata B Rao Signed-off-by: David Gibson --- hw/ppc/spapr_cpu_core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

[Qemu-devel] [PULL 03/23] ppc: Use a helper to filter writes to LPCR

From: Benjamin Herrenschmidt This handles filtering bits based on what is implemented by a given architecture version. We also use it to copy to LPCR some of the relevant 970 HID4 bits. Signed-off-by: Benjamin Herrenschmidt [clg: fixed

[Qemu-devel] [PULL 12/23] target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb

From: Aaron Larson Eliminate redundant and incorrect booke206_page_size_to_tlb function from ppce500_spin.c in preference to previously existing but newly exported definition from e500.c Defect analysis: The booke206_page_size_to_tlb function in e500.c was updated in commit

[Qemu-devel] [PULL 20/23] spapr: drop reference on child object during core realization

From: Greg Kurz When a core is being realized, we create a child object for each thread of the core. The child is first initialized with object_initialize() which sets its ref count to 1, and then added to the core with object_property_add_child() which bumps the ref count to 2.

[Qemu-devel] [PULL 15/23] ppc/xics: Move SPAPR specific code to a separate file

From: Benjamin Herrenschmidt Leave the core ICP/ICS logic in xics.c and move the top level class wrapper, hypercall and RTAS handlers to xics_spapr.c Signed-off-by: Benjamin Herrenschmidt [add cpu.h in xics_spapr.c, move set_nr_irqs and

[Qemu-devel] [PATCH 4/4] ppc: fix VRMA support

commit 08109fd4360d ('ppc: Add proper real mode translation support') introduced VRMA support for which SLB entries need to be created. But it did not take into account the changes in ppc_slb_t and missed the setting of the segment page size attribute. However, gcc spotted it :

Re: [Qemu-devel] [PATCH 2/2] ppc: Fix 64K pages support in full emulation

On 07/01/2016 12:13 AM, Benjamin Herrenschmidt wrote: > On Thu, 2016-06-30 at 18:01 +0200, Cédric Le Goater wrote: >> +static uint32_t ppc_hash64_pte_size_decode(PowerPCCPU *cpu, uint64_t >> pte0, >> + uint64_t pte1, uint32_t >> slb_pshift) >> { >> -

[Qemu-devel] [PULL 00/23] ppc-for-2.7 queue 20160701

The following changes since commit 8a0b4de048e20215415b24c7b42514c27b9d6ef3: pcspk: fix KVM (2016-06-30 19:00:02 +0100) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.7-20160701 for you to fetch changes up

[Qemu-devel] [PULL 23/23] qmp: fix spapr example of query-hotpluggable-cpus

From: Igor Mammedov 27393c33 qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore added -id suffix to property names but forgot to fix example in qmp-commands.hx Fix example to have 'core-id' instead of 'core' to match current code Signed-off-by: Igor

[Qemu-devel] [PULL 19/23] spapr: Restore support for 970MP and POWER8NVL CPU cores

From: Bharata B Rao Introduction of core based CPU hotplug for PowerPC sPAPR didn't add support for 970MP and POWER8NVL based core types. Add support for the same. While we are here, add support for explicit specification of POWER5+_v2.1 core type. Signed-off-by:

[Qemu-devel] [PULL 01/23] ppc: Add a bunch of hypervisor SPRs to Book3s

From: Benjamin Herrenschmidt We don't give them a KVM reg number yet as no current KVM version supports HV mode. Signed-off-by: Benjamin Herrenschmidt [clg: SPRs AMOR,DAWR,DARWX were already included in commit f401dd32cb8e9] Signed-off-by:

[Qemu-devel] [PULL 14/23] ppc/xics: Rename existing xics to xics_spapr

From: Benjamin Herrenschmidt The common class doesn't change, the KVM one is sPAPR specific. Rename variables and functions to xics_spapr. Retain the type name as "xics" to preserve migration for existing sPAPR guests. Signed-off-by: Benjamin Herrenschmidt

[Qemu-devel] [PULL 17/23] ppc/xics: Replace "icp" with "xics" in most places

From: Benjamin Herrenschmidt The "ICP" is a different object than the "XICS". For historical reasons, we have a number of places where we name a variable "icp" while it contains a XICSState pointer. There *is* an ICPState structure too so this makes the code really

[Qemu-devel] [PATCH 0/4] ppc: fixes for large page and VRMA support

Here is a little serie with API cleanups and fixes for large page and VRMA. Previous patches which added the support did not take into account the segment page size attribute. Cédric Le Goater (4): ppc: simplify ppc_hash64_hpte_page_shift_noslb() ppc: fix large page support ppc: simplify

[Qemu-devel] [PATCH 1/4] ppc: simplify ppc_hash64_hpte_page_shift_noslb()

The segment page shift parameter is never used. Let's remove it. Signed-off-by: Cédric Le Goater --- hw/ppc/spapr_hcall.c| 4 ++-- target-ppc/mmu-hash64.c | 6 +- target-ppc/mmu-hash64.h | 3 +-- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git

[Qemu-devel] [PATCH 2/4] ppc: fix large page support

A regression was introduced by commit 53df75a59bcf ('ppc: Fix 64K pages support in full emulation'). ppc_hash64_hpte_page_shift_noslb() should be used to compute the page size. Signed-off-by: Cédric Le Goater --- target-ppc/mmu-hash64.c | 24 +--- 1 file

[Qemu-devel] [PATCH 3/4] ppc: simplify ppc_hash64_pteg_search()

The page shift parameter is never used. Let's remove it. Signed-off-by: Cédric Le Goater --- target-ppc/mmu-hash64.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index fdaff9e874ba..7ef45ee53bf5

[Qemu-devel] [PATCH v2 1/2] gic: provide defines for v2/v3 targetlist sizes

Signed-off-by: Andrew Jones --- include/hw/intc/arm_gic.h | 3 +++ include/hw/intc/arm_gicv3_common.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 0971e37710dd6..42bb535fd4571 100644 ---

Re: [Qemu-devel] [PATCH for-2.7] aux: Rename aux.[ch] to auxbus.[ch] for the benefit of Windows

On 07/01/2016 06:45 AM, Peter Maydell wrote: > On Windows 'aux.*' is a reserved name and cannot be used for > filenames; see > > https://msdn.microsoft.com/en-gb/library/windows/desktop/aa365247(v=vs.85).aspx > > This prevents cloning the QEMU git repo on Windows: > > C:\Java\sources\kvm> git

Re: [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation

On 07/01/2016 04:57 PM, Laszlo Ersek wrote: On 06/30/16 21:07, Marcel Apfelbaum wrote: 64-bit BARs allocations fix for devices behind PXBs/PXB-PCIEs. In build_crs() the calculation and merging of the ranges already happens in 64-bit, but the entry boundaries are silently truncated to 32-bit in

Re: [Qemu-devel] [Qemu-ppc] [PATCH v0] spapr: Ensure thread0 of CPU core is always realized first

On Fri, 1 Jul 2016 10:44:39 +0530 Bharata B Rao wrote: > During CPU core realization, we create all the thread objects and parent > them to the core object in a loop. However, the realization of thread > objects is done separately by walking the threads of a core

Re: [Qemu-devel] [PATCH] hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT

On 1 July 2016 at 13:40, Andrew Jones wrote: > On Thu, Jun 30, 2016 at 03:09:53PM +0100, Peter Maydell wrote: >> On 28 June 2016 at 18:14, Ard Biesheuvel wrote: >> > Since QEMU performs cacheable accesses to guest memory when doing DMA >> > as part

[Qemu-devel] [PATCH v2 2/2] hw/arm/virt: tcg: adjust MPIDR like KVM

KVM adjusts the MPIDR of guest vcpus based on the architecture of the host, 32-bit vs. 64-bit, and, for 64-bit, also on the type of GIC the guest is using. To be consistent and improve SGI efficiency we make the same adjustments for TCG as 64-bit KVM hosts. We neglect to add consistency with

Re: [Qemu-devel] [PULL 00/23] ppc-for-2.7 queue 20160701

m/dgibson/qemu.git tags/ppc-for-2.7-20160701 > > for you to fetch changes up to 13f5e8003e7b67039cb7a19e41b4f7f7ac669cb3: > > qmp: fix spapr example of query-hotpluggable-cpus (2016-07-01 13:41:47 > +1000) > > >

Re: [Qemu-devel] [PATCH] linux-user: fix signal() syscall on x86_64

On 1 July 2016 at 12:59, Wirth, Allan wrote: > Linux on X86_64 does not use sel_arg_struct for select(), the args are > passed directly. This patch switches a define so X86_64 uses the correct > calling convention. > > Signed-off-by: Allan Wirth > --- >

Re: [Qemu-devel] [PATCH V4 0/6] pxb: fix 64-bit MMIO allocation

On 06/30/16 21:07, Marcel Apfelbaum wrote: > 64-bit BARs allocations fix for devices behind PXBs/PXB-PCIEs. > > In build_crs() the calculation and merging of the ranges already happens > in 64-bit, but the entry boundaries are silently truncated to 32-bit in the > call to aml_dword_memory(). Fix

Re: [Qemu-devel] [PATCH 00/17] s390x: the big pci update

On Fri, 24 Jun 2016 15:28:49 +0200 Cornelia Huck wrote: > We had been looking at remodelling the pci representation for s390x > to handle our slightly odd architecture correctly some time ago > already, but now we have a patchset that we're happy with. > > There's a

[Qemu-devel] [PATCH v2 0/2] hw/arm/virt: tcg: adjust MPIDR almost-like KVM

In some ways this v2 is more of an RFC then the initial posting, which had a different subject, and is here [*]. In this version we point out the real [current] goal, which is to get the guest MPIDR consistent with KVM. However, what's debatable is we purposefully neglect 32-bit consistency, as

[Qemu-devel] [Bug 1598029] [NEW] failed to boot a customized kernel if emulating Broadwell/Skylake

Public bug reported: Hardware: X86-64, Intel(R) Core(TM) i7-6500U( Skylake) OS: Linux Mint 18 Host Kernel: 4.5.7 + PaX/Grsecurity Qemu: QEMU emulator version 2.5.0 (Debian 1:2.5+dfsg-5ubuntu10.2) [Reproduction Steps] 1, Install a Debian 8 in the guest 2, Install a customized kernel( using same

[Qemu-devel] [PATCH] linux-user: fix signal() syscall on x86_64

Linux on X86_64 does not use sel_arg_struct for select(), the args are passed directly. This patch switches a define so X86_64 uses the correct calling convention. Signed-off-by: Allan Wirth --- linux-user/syscall.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [Qemu-devel] [PATCH] hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT

On 1 July 2016 at 12:40, Andrew Jones wrote: > I might have mentioned in the commit message that the ACPI generation > already does this, as _CCA is set to 1, added with commit bc64b96c > (assuming I'm right, and a value of 1 there is the ACPI equivalent of > this patch) > >

Re: [Qemu-devel] [PATCH RFC] fixup! tests: New make target check-source

Markus Armbruster writes: > Sascha Silbe writes: > >> Dear Markus, >> >> Markus Armbruster writes: >> >>> --- >>> tests/header-test-template.c | 16 >> [...] >> >> Thanks, that helped, I get a bit further now. >>

Re: [Qemu-devel] [Bug 1594239] Re: After adding more scsi disks for Aarch64 virtual machine, start the VM and got Qemu Error

Thanks! That makes sense. But, off the cuff, it seems odd that there's an instance_id if it can only be zero. But then again, it may be overloaded or be applicable in other cases. I'll dig into the code today. On 07/01/2016 02:27 AM, Dr. David Alan Gilbert wrote: > Hi Tom, >Yeh it's just

Re: [Qemu-devel] [PATCH 3/3] hid.c: Add debug support

On 06/30/2016 03:32 PM, John Arbuckle wrote: > Add debug macros to the code for easier debugging. > > Signed-off-by: John Arbuckle > --- > hw/input/hid.c | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/hw/input/hid.c b/hw/input/hid.c > index

[Qemu-devel] [PATCH v9 03/10] target-avr: adding a sample AVR board

Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 ++ hw/avr/Makefile.objs | 21 + hw/avr/sample-io.c | 227 +++ hw/avr/sample.c | 116 ++ 4 files changed, 370 insertions(+) create

[Qemu-devel] [PATCH v9 00/10] 8bit AVR cores

This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support

[Qemu-devel] [PATCH v9 07/10] target-avr: adding instruction decoder

Signed-off-by: Michael Rolnik --- target-avr/decode.c | 693 1 file changed, 693 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644 index

[Qemu-devel] [PATCH v9 02/10] target-avr: adding AVR CPU features/flavors

Signed-off-by: Michael Rolnik --- target-avr/cpu.c | 307 ++- target-avr/cpu.h | 53 + target-avr/machine.c | 1 + 3 files changed, 360 insertions(+), 1 deletion(-) diff --git a/target-avr/cpu.c

[Qemu-devel] [PATCH v9 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions 4. saving sreg, rampD, rampX, rampY, rampD, eind in HW representation savin

Signed-off-by: Michael Rolnik --- arch_init.c | 2 + configure | 5 + default-configs/avr-softmmu.mak | 21 +++ include/disas/bfd.h | 6 + include/sysemu/arch_init.h | 1 + target-avr/Makefile.objs|

[Qemu-devel] [PATCH v9 05/10] target-avr: adding AVR interrupt handling

Signed-off-by: Michael Rolnik --- target-avr/helper.c | 59 - 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/target-avr/helper.c b/target-avr/helper.c index 3e23646..060b2f0 100644 --- a/target-avr/helper.c +++

[Qemu-devel] [PATCH v9 09/10] target-avr: updating translate.c to use instructions translation

Signed-off-by: Michael Rolnik --- target-avr/Makefile.objs | 4 +- target-avr/translate.c | 142 --- 2 files changed, 64 insertions(+), 82 deletions(-) diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs index

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