Re: [Qemu-devel] [PATCH 2/2] cpu-exec: remove tb_lock from the hot-path

On 05/07/2016 13:14, Alex Bennée wrote: > /* > * Patch the last TB with a jump to the current TB. > * > * Modification of the TB has to be protected with tb_lock which can > * either be already held or taken here. > */ > static inline void maybe_patch_last_tb(CPUState *cpu, >

Re: [Qemu-devel] [PULL 0/8] ipxe: update submodule from 4e03af8ec to 041863191

On 4 July 2016 at 07:30, Gerd Hoffmann wrote: > Hi, > > Here comes the ipxe update for 2.7, rebasing the ipxe module to latest > master and also adding boot roms for e1000e and vmxnet3. > > v2: two incremental tweaks to make sure the two new roms are installed > properly. > >

Re: [Qemu-devel] [RFC PATCH v0 2/5] cpu: Optionally use arch_id instead of cpu_index in cpu vmstate_register()

On Tue, Jul 05, 2016 at 09:15:51AM +0200, Igor Mammedov wrote: > On Tue, 5 Jul 2016 10:12:49 +0530 > Bharata B Rao wrote: > > > Introduce CPUState.prefer_arch_id_over_cpu_index and > > MachineClass.prefer_arch_id_over_cpu_index that allow target > > machines to

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

* Michael S. Tsirkin (m...@redhat.com) wrote: > On Tue, Jul 05, 2016 at 12:59:42PM +0200, Paolo Bonzini wrote: > > > > > > On 05/07/2016 12:06, Michael S. Tsirkin wrote: > > > > -m 2G,slots=16,maxmem=2T > > > > > > > > On a host with a 39bit physaddress limit do you error > > > > on that

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Tue, Jul 05, 2016 at 01:46:58PM +0200, Paolo Bonzini wrote: > > > On 05/07/2016 13:09, Michael S. Tsirkin wrote: > > > How do you handle migration in the above scenario from say 46bit host to > > > 39bit host, where the firmware has mapped (while running on the source) > > > a 64-bit BAR

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Tue, Jul 05, 2016 at 10:49:48AM +0100, Dr. David Alan Gilbert wrote: > * Daniel P. Berrange (berra...@redhat.com) wrote: > > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) > > wrote: > > > From: "Dr. David Alan Gilbert" > > > > > > QEMU sets the

Re: [Qemu-devel] [PATCH v3 1/1] target-arm: Use Neon for zero checking

On Sat, Jul 2, 2016 at 3:37 AM, Richard Henderson wrote: > On 06/30/2016 06:45 AM, Peter Maydell wrote: >> >> On 29 June 2016 at 09:47, wrote: >>> >>> From: Vijay >>> >>> Use Neon instructions to perform zero checking of >>> buffer.

Re: [Qemu-devel] [PATCH for-2.7 7/8] s390x/css: Factor out virtual css bridge and bus

On Tue, 5 Jul 2016 16:30:35 +0800 Jing Liu wrote: > Dear Conny, > > On 07/05/2016 03:56 PM, Cornelia Huck wrote: > > > + > > +static const TypeInfo virtual_css_bridge_info = { > > +.name = TYPE_VIRTUAL_CSS_BRIDGE, > > +.parent=

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On Tue, Jul 05, 2016 at 01:45:10PM +0200, Paolo Bonzini wrote: > > > On 05/07/2016 12:07, Daniel P. Berrange wrote: > >> > What the final default behavior will be is not clear yet. Not enabled? > >> > Enabled in case no VGA is present? Enabled unconditionally (simliar to > >> > ovmf)? > >

Re: [Qemu-devel] [PATCH v2 5/6] x86: fix up 32 bit phys_bits case

On Tue, Jul 05, 2016 at 12:29:30PM +0100, Dr. David Alan Gilbert wrote: > * Daniel P. Berrange (berra...@redhat.com) wrote: > > On Mon, Jul 04, 2016 at 08:16:08PM +0100, Dr. David Alan Gilbert (git) > > wrote: > > > From: "Dr. David Alan Gilbert" > > > > > > On 32 bit

Re: [Qemu-devel] [PULL 00/14] ppc-for-2.7 queue 20160705 (v2)

> > are available in the git repository at: > > git://github.com/dgibson/qemu.git tags/ppc-for-2.7-20160705 > > for you to fetch changes up to 2c7ad80443e9747eb85b508be01cded958191bad: > > ppc/hash64: Fix suppo

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On 05/07/2016 13:09, Michael S. Tsirkin wrote: > > How do you handle migration in the above scenario from say 46bit host to > > 39bit host, where the firmware has mapped (while running on the source) > > a 64-bit BAR above the destination's maximum physical address? > > Again management would

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On 05/07/2016 12:07, Daniel P. Berrange wrote: >> > What the final default behavior will be is not clear yet. Not enabled? >> > Enabled in case no VGA is present? Enabled unconditionally (simliar to >> > ovmf)? > (Bitter) experiance in libvirt has shown us that magically enabling > things

Re: [Qemu-devel] [PATCH v2 5/6] x86: fix up 32 bit phys_bits case

* Daniel P. Berrange (berra...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:08PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > On 32 bit systems fix up phys_bits to be consistent with what > > we tell the guest; don't ever bother

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On 05/07/2016 12:00, Gerd Hoffmann wrote: > One option would be to continue using sgabios.bin in fw_cfg. But > instead of loading and executing it activate the build-in serial console > if we find the file. That would make the switch completely transparent > to upper layers. But it is quite

Re: [Qemu-devel] [PATCH 2/2] cpu-exec: remove tb_lock from the hot-path

Emilio G. Cota writes: > On Mon, Jul 04, 2016 at 12:45:52 +0100, Alex Bennée wrote: >> >> Emilio G. Cota writes: >> >> > On Fri, Jul 01, 2016 at 17:16:10 +0100, Alex Bennée wrote: >> >> Lock contention in the hot path of moving between existing patched >> >>

Re: [Qemu-devel] [PATCH 08/24] vhost-user: return a read error

On Tue, Jul 05, 2016 at 11:18:38AM +0200, Marc-André Lureau wrote: > Hi > > On Tue, Jul 5, 2016 at 12:35 AM, Michael S. Tsirkin wrote: > > On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote: > >> Hi > >> > >> On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Tue, Jul 05, 2016 at 12:59:42PM +0200, Paolo Bonzini wrote: > > > On 05/07/2016 12:06, Michael S. Tsirkin wrote: > > > -m 2G,slots=16,maxmem=2T > > > > > > On a host with a 39bit physaddress limit do you error > > > on that or not? I think oVirt is currently doing something > > >

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On 05/07/2016 12:06, Michael S. Tsirkin wrote: > > -m 2G,slots=16,maxmem=2T > > > > On a host with a 39bit physaddress limit do you error > > on that or not? I think oVirt is currently doing something > > similar to that, but I'm trying to get confirmation. > > That would only be a

[Qemu-devel] [PATCH v1 0/2] Use GChecksum as fallback hash impl

This uses the GChecksum APIs as final hash impl, instead of a no-op stub. This lets us remove conditional registration of the quorum driver. Daniel P. Berrange (2): crypto: use glib as fallback for hash algorithm Revert "block: don't register quorum driver if SHA256 support is

[Qemu-devel] [PATCH v1 2/2] Revert "block: don't register quorum driver if SHA256 support is unavailable"

The qcrypto hash APIs now guarantee that sha256 is available at compile time, so skipping registration is rarely needed. A check at time of open is kept to ensure good error reporting in the (unlikely) case sha256 is runtime disabled. This reverts commit e94867ed5f241008d0f53142b2704a075f9ed505.

[Qemu-devel] [PATCH v1 1/2] crypto: use glib as fallback for hash algorithm

GLib >= 2.16 provides GChecksum API which is good enough for md5, sha1, sha256 and sha512. Use this as a final fallback if neither nettle or gcrypt are available. This lets us remove the stub hash impl, and so callers can be sure those 4 algs are always available at compile time. They may still be

Re: [Qemu-devel] [PATCH v2 6/6] x86: Add sanity checks on phys_bits

* Eduardo Habkost (ehabk...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:09PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > Add some sanity checks on the phys-bits setting now that > > the user can set it. > >a) That it's in

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Tue, Jul 05, 2016 at 11:13:26AM +0100, Dr. David Alan Gilbert wrote: > * Michael S. Tsirkin (m...@redhat.com) wrote: > > On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote: > > > * Michael S. Tsirkin (m...@redhat.com) wrote: > > > > On Mon, Jul 04, 2016 at 08:16:03PM +0100,

Re: [Qemu-devel] [PATCH v8 7/7] trace: Add QAPI/QMP interfaces to query and control per-vCPU tracing state

Eric Blake writes: > On 07/04/2016 03:41 AM, Lluís Vilanova wrote: >> Signed-off-by: Lluís Vilanova >> Reviewed-by: Stefan Hajnoczi >> --- >> hmp-commands-info.hx |6 +- >> hmp-commands.hx |7 +- >> monitor.c| 17 +- >>

[Qemu-devel] [RFC PATCH V3 0/3] filter-rewriter: introduce filter-rewriter

Filter-rewriter is a part of COLO project. So this patch set depend on colo-compare. It will rewrite some of secondary packet to make secondary guest's connection established successfully. In this module we will rewrite tcp packet's ack to the secondary from primary,and rewrite tcp packet's seq to

[Qemu-devel] [RFC PATCH V3 1/3] filter-rewriter: introduce filter-rewriter initialization

Filter-rewriter is a part of COLO project. It will rewrite some of secondary packet to make secondary guest's tcp connection established successfully. In this module we will rewrite tcp packet's ack to the secondary from primary,and rewrite tcp packet's seq to the primary from secondary. usage:

[Qemu-devel] [RFC PATCH V3 3/3] filter-rewriter: rewrite tcp packet to keep secondary connection

We will rewrite tcp packet secondary received and sent. When colo guest is a tcp server. Firstly, client start a tcp handshake. the packet's seq=client_seq, ack=0,flag=SYN. COLO primary guest get this pkt and mirror(filter-mirror) to secondary guest, secondary get it use filter-redirector.

[Qemu-devel] [RFC PATCH V3 2/3] filter-rewriter: track connection and parse packet

We use colo-base.h to track connection and parse packet Signed-off-by: Zhang Chen Signed-off-by: Li Zhijian Signed-off-by: Wen Congyang --- net/filter-rewriter.c | 50

Re: [Qemu-devel] [RFC 00/13] Live memory snapshot based on userfaultfd

On 2016/7/5 17:57, Baptiste Reynal wrote: On Tue, Jul 5, 2016 at 3:49 AM, Hailiang Zhang wrote: On 2016/7/4 20:22, Baptiste Reynal wrote: On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang wrote: For now, we still didn't support

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

* Michael S. Tsirkin (m...@redhat.com) wrote: > On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote: > > * Michael S. Tsirkin (m...@redhat.com) wrote: > > > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) > > > wrote: > > > > From: "Dr. David Alan

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On Tue, Jul 05, 2016 at 12:00:48PM +0200, Gerd Hoffmann wrote: > On Di, 2016-07-05 at 09:06 +0100, Daniel P. Berrange wrote: > > On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > Next round of patches. Changes: > > > > > > * Moved it all to a new sercon.c

Re: [Qemu-devel] [PULL 00/36] pc, pci, virtio: new features, cleanups, fixes

On 4 July 2016 at 17:46, Michael S. Tsirkin wrote: > The following changes since commit e2c8f9e44e07d8210049abaa6042ec3c956f1dd4: > > Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into > staging (2016-07-04 10:49:17 +0100) > > are available in the git

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Tue, Jul 05, 2016 at 10:33:25AM +0100, Dr. David Alan Gilbert wrote: > * Michael S. Tsirkin (m...@redhat.com) wrote: > > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) > > wrote: > > > From: "Dr. David Alan Gilbert" > > > > > > QEMU sets the

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, Jul 05, 2016 at 10:26:56AM +0100, Daniel P. Berrange wrote: > On Tue, Jul 05, 2016 at 11:18:29AM +0200, Alberto Garcia wrote: > > On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote: > > > > > The point of using qcrypto_hash_supports() is that it isolates the > > > block code

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On Di, 2016-07-05 at 09:06 +0100, Daniel P. Berrange wrote: > On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote: > > Hi, > > > > Next round of patches. Changes: > > > > * Moved it all to a new sercon.c file. > > * Code maps cp437 to utf8 now, giving a much nicer display.

Re: [Qemu-devel] [RFC 00/13] Live memory snapshot based on userfaultfd

On Tue, Jul 5, 2016 at 3:49 AM, Hailiang Zhang wrote: > On 2016/7/4 20:22, Baptiste Reynal wrote: >> >> On Thu, Jan 7, 2016 at 1:19 PM, zhanghailiang >> wrote: >>> >>> For now, we still didn't support live memory snapshot, we have

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

* Daniel P. Berrange (berra...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > QEMU sets the guests physical address bits to 40; this is wrong > > on most hardware, and can be

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > QEMU sets the guests physical address bits to 40; this is wrong > on most hardware, and can be detected by the guest. > It also stops you using really huge

Re: [Qemu-devel] [PATCH v2 5/6] x86: fix up 32 bit phys_bits case

On Mon, Jul 04, 2016 at 08:16:08PM +0100, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > On 32 bit systems fix up phys_bits to be consistent with what > we tell the guest; don't ever bother with using the phys_bits > property. > @@ -2990,6 +2986,15

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, Jul 05, 2016 at 04:57:58PM +0800, Fam Zheng wrote: > On Tue, 07/05 09:45, Daniel P. Berrange wrote: > > On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote: > > > This was the only exceptional module init function that does something > > > else than a simple list of bdrv_register()

Re: [Qemu-devel] [PATCH v2 0/6] x86: Physical address limit patches

* Michael S. Tsirkin (m...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:03PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > QEMU sets the guests physical address bits to 40; this is wrong > > on most hardware, and can be detected

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, Jul 05, 2016 at 11:18:29AM +0200, Alberto Garcia wrote: > On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote: > > > The point of using qcrypto_hash_supports() is that it isolates the > > block code Makefile rules from the details of the current specific > > impl of the hash

Re: [Qemu-devel] [PATCH 08/24] vhost-user: return a read error

Hi On Tue, Jul 5, 2016 at 12:35 AM, Michael S. Tsirkin wrote: > On Mon, Jul 04, 2016 at 11:56:56PM +0200, Marc-André Lureau wrote: >> Hi >> >> On Mon, Jul 4, 2016 at 5:47 PM, Michael S. Tsirkin wrote: >> > Why does vhost_user_set_log_base need to return error?

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue 05 Jul 2016 10:45:21 AM CEST, Daniel P. Berrange wrote: > The point of using qcrypto_hash_supports() is that it isolates the > block code Makefile rules from the details of the current specific > impl of the hash APIs in QEMU. As a prime example of why this is > important, try rebasing to

[Qemu-devel] [PATCH] block/gluster: add support to choose libgfapi logfile

currently all the libgfapi logs defaults to '/dev/stderr' as it was hardcoded in a call to glfs logging api, in case if debug level is chosen to DEBUG/TRACE gfapi logs will be huge and fill/overflow the console view. this patch provides a commandline option to mention log file path which helps in

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

Dear Alberto, Alberto Garcia writes: > On Tue 05 Jul 2016 09:58:25 AM CEST, Sascha Silbe wrote: > >> The quorum driver needs SHA256 which was introduced in gnutls 2.11.1. > > Are you sure about that? > > * Version 1.7.4 (released 2007-02-05) > > [...] > > ** API and ABI

Re: [Qemu-devel] [PATCH for-2.7? 0/3] Two coroutine tweaks

On Mon, 07/04 19:09, Paolo Bonzini wrote: > Hi, > > I meant to send these close to soft freeze because the final patch is > prone to conflicts, but it turns out I didn't send them. Still they're > pretty mechanical so I'm shooting them out now. Any thoughts? I didn't review patch 3 line by

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, 07/05 09:45, Daniel P. Berrange wrote: > On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote: > > This was the only exceptional module init function that does something > > else than a simple list of bdrv_register() calls, in all the block > > drivers. > > > > The

Re: [Qemu-devel] [PULL 0/1] Revert "bios: Add fast variant of SeaBIOS for use with -kernel on x86."

On 4 July 2016 at 16:26, Gerd Hoffmann wrote: > Hi, > > Reverts patch and also remove pc-bios/bios-fast.bin. > > please pull, > Gerd > > The following changes since commit 3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa: > > Merge remote-tracking branch >

[Qemu-devel] [PATCH v11 26/28] intel_iommu: support all masks in interrupt entry cache invalidation

From: Radim Krčmář Linux guests do not gracefully handle cases when the invalidation mask they wanted is not supported, probably because real hardware always allowed all. We can just say that all 16 masks are supported, because both ioapic_iec_notifier and

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, Jun 28, 2016 at 09:47:47AM +0800, Fam Zheng wrote: > This was the only exceptional module init function that does something > else than a simple list of bdrv_register() calls, in all the block > drivers. > > The qcrypto_hash_supports is actually a static check, determined at > compile

[Qemu-devel] [PATCH v11 25/28] kvm-irqchip: do explicit commit when update irq

In the past, we are doing gsi route commit for each irqchip route update. This is not efficient if we are updating lots of routes in the same time. This patch removes the committing phase in kvm_irqchip_update_msi_route(). Instead, we do explicit commit after all routes updated. Signed-off-by:

[Qemu-devel] [PATCH v11 28/28] intel_iommu: disallow kernel-irqchip=on with IR

When user specify "kernel-irqchip=on", throw error and then quit. Signed-off-by: Peter Xu Reviewed-by: Paolo Bonzini --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c

[Qemu-devel] [PATCH v11 27/28] kvm-all: add trace events for kvm irqchip ops

These will help us monitoring irqchip route activities more easily. Signed-off-by: Peter Xu Reviewed-by: Paolo Bonzini --- kvm-all.c| 5 + trace-events | 3 +++ 2 files changed, 8 insertions(+) diff --git a/kvm-all.c b/kvm-all.c index

[Qemu-devel] [PATCH v11 24/28] kvm-irqchip: x86: add msi route notify fn

One more IEC notifier is added to let msi routes know about the IEC changes. When interrupt invalidation happens, all registered msi routes will be updated for all PCI devices. Since both vfio and vhost are possible gsi route consumers, this patch will go one step further to keep them safe in

[Qemu-devel] [PATCH v11 21/28] intel_iommu: add SID validation for IR

This patch enables SID validation. Invalid interrupts will be dropped. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 69 --- include/hw/i386/intel_iommu.h | 17 +++ 2 files changed, 75 insertions(+), 11

[Qemu-devel] [PATCH v11 23/28] kvm-irqchip: i386: add hook for add/remove virq

Adding two hooks to be notified when adding/removing msi routes. There are two kinds of MSI routes: - in kvm_irqchip_add_irq_route(): before assigning IRQFD. Used by vhost, vfio, etc. - in kvm_irqchip_send_msi(): when sending direct MSI message, if direct MSI not allowed, we will first

[Qemu-devel] [PATCH v11 17/28] intel_iommu: add support for split irqchip

In split irqchip mode, IOAPIC is working in user space, only update kernel irq routes when entry changed. When IR is enabled, we directly update the kernel with translated messages. It works just like a kernel cache for the remapping entries. Since KVM irqfd is using kernel gsi routes to deliver

[Qemu-devel] [PATCH v11 22/28] kvm-irqchip: simplify kvm_irqchip_add_msi_route

Changing the original MSIMessage parameter in kvm_irqchip_add_msi_route into the vector number. Vector index provides more information than the MSIMessage, we can retrieve the MSIMessage using the vector easily. This will avoid fetching MSIMessage every time before adding MSI routes. Meanwhile,

[Qemu-devel] [PATCH v11 15/28] q35: ioapic: add support for emulated IOAPIC IR

This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by

[Qemu-devel] [PATCH v11 20/28] intel_iommu: Add support for Extended Interrupt Mode

From: Jan Kiszka As neither QEMU nor KVM support more than 255 CPUs so far, this is simple: we only need to switch the destination ID translation in vtd_remap_irq_get if EIME is set. Once CFI support is there, it will have to take EIM into account as well. So far,

Re: [Qemu-devel] [PATCH v2 4/6] x86: Set physical address bits based on host

* Eduardo Habkost (ehabk...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:07PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > A special case based on the previous phys-bits property; if it's > > the magic value 0 then use the hosts

[Qemu-devel] [PATCH v11 14/28] intel_iommu: Add support for PCI MSI remap

This patch enables interrupt remapping for PCI devices. To play the trick, one memory region "iommu_ir" is added as child region of the original iommu memory region, covering range 0xfeeX (which is the address range for APIC). All the writes to this range will be taken as MSI, and translation

[Qemu-devel] [PATCH v11 19/28] ioapic: register IOMMU IEC notifier for ioapic

Let IOAPIC the first consumer of x86 IOMMU IEC invalidation notifiers. This is only used for split irqchip case, when vIOMMU receives IR invalidation requests, IOAPIC will be notified to update kernel irq routes. For simplicity, we just update all IOAPIC routes, even if the invalidated entries are

Re: [Qemu-devel] [PATCH v2 3/6] x86: fill high bits of mtrr mask

* Eduardo Habkost (ehabk...@redhat.com) wrote: > On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote: > [...] > > @@ -2084,6 +2085,27 @@ static int kvm_get_msrs(X86CPU *cpu) > > } > > > > assert(ret == cpu->kvm_msr_buf->nmsrs); > > +/* > > + * MTRR

[Qemu-devel] [PATCH v11 13/28] intel_iommu: add IR translation faults defines

Adding translation fault definitions for interrupt remapping. Please refer to VT-d spec section 7.1. Signed-off-by: Peter Xu --- hw/i386/intel_iommu_internal.h | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h

Re: [Qemu-devel] [PULL 0/8] ipxe: update submodule from 4e03af8ec to 041863191

On 04/07/2016 14:58, Gerd Hoffmann wrote: > On Mo, 2016-07-04 at 13:38 +0100, Peter Maydell wrote: >> On 4 July 2016 at 07:30, Gerd Hoffmann wrote: >>> Hi, >>> >>> Here comes the ipxe update for 2.7, rebasing the ipxe module to latest >>> master and also adding boot roms

[Qemu-devel] [PATCH v11 18/28] x86-iommu: introduce IEC notifiers

This patch introduces x86 IOMMU IEC (Interrupt Entry Cache) invalidation notifier list. When vIOMMU receives IEC invalidate request, all the registered units will be notified with specific invalidation requests. Intel IOMMU is the first provider that generates such a event. Signed-off-by: Peter

[Qemu-devel] [PATCH v11 12/28] intel_iommu: define several structs for IOMMU IR

Several data structs are defined to better support the rest of the patches: IRTE to parse remapping table entries, and IOAPIC/MSI related structure bits to parse interrupt entries to be filled in by guest kernel. Signed-off-by: Peter Xu --- include/hw/i386/intel_iommu.h | 74

[Qemu-devel] [PATCH v11 09/28] acpi: add DMAR scope definition for root IOAPIC

To enable interrupt remapping for intel IOMMU device, each IOAPIC device in the system reported via ACPI MADT must be explicitly enumerated under one specific remapping hardware unit. This patch adds the root-complex IOAPIC into the default DMAR device. Please refer to VT-d spec 8.3.1.1 for more

Re: [Qemu-devel] [PATCH] char: do not use atexit cleanup handler

On 04/07/2016 21:53, Gerd Hoffmann wrote: > Hi, > What about graphics threads ? In particular I'd be thinking of spice which uses threads and chardevs. >>> >>> I think it should be quiesced after pause_all_vcpus returns. Marc-André >>> should know, but it's better to check with

[Qemu-devel] [PATCH v11 16/28] ioapic: introduce ioapic_entry_parse() helper

Abstract IOAPIC entry parsing logic into a helper function. Signed-off-by: Peter Xu --- hw/intc/ioapic.c | 110 +++ 1 file changed, 54 insertions(+), 56 deletions(-) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue 05 Jul 2016 09:58:25 AM CEST, Sascha Silbe wrote: > The quorum driver needs SHA256 which was introduced in gnutls 2.11.1. Are you sure about that? * Version 1.7.4 (released 2007-02-05) [...] ** API and ABI modifications: GNUTLS_MAC_SHA256, GNUTLS_MAC_SHA384, GNUTLS_MAC_SHA512: New

[Qemu-devel] [PATCH v11 10/28] intel_iommu: define interrupt remap table addr register

Defined Interrupt Remap Table Address register to store IR table pointer. Also, do proper handling on global command register writes to store table pointer and its size. One more debug flag "DEBUG_IR" is added for interrupt remapping. Signed-off-by: Peter Xu ---

[Qemu-devel] [PATCH v11 06/28] acpi: enable INTR for DMAR report structure

In ACPI DMA remapping report structure, enable INTR flag when specified. Signed-off-by: Peter Xu --- hw/i386/acpi-build.c | 14 +- include/hw/i386/intel_iommu.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c

[Qemu-devel] [PATCH v11 11/28] intel_iommu: handle interrupt remap enable

Handle writting to IRE bit in global command register. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 20 1 file changed, 20 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c793031..a12091e 100644 ---

[Qemu-devel] [PATCH v11 07/28] intel_iommu: allow queued invalidation for IR

Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: Peter Xu ---

[Qemu-devel] [PATCH v11 05/28] x86-iommu: introduce "intremap" property

Adding one property for intel-iommu devices to specify whether we should support interrupt remapping. By default, IR is disabled. To enable it, we should use (take Intel IOMMU as example): -device intel_iommu,intremap=on This property can be shared by Intel and future AMD IOMMUs.

[Qemu-devel] [PATCH v11 04/28] x86-iommu: q35: generalize find_add_as()

Remove VT-d calls in common q35 codes. Instead, we provide a general find_add_as() for x86-iommu type. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 15 --- include/hw/i386/intel_iommu.h | 5 - include/hw/i386/x86-iommu.h | 3 +++ 3 files

[Qemu-devel] [PATCH v11 08/28] intel_iommu: set IR bit for ECAP register

Enable IR in IOMMU Extended Capability register. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 6 ++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8ea408d..3d99544

[Qemu-devel] [PATCH v11 03/28] x86-iommu: provide x86_iommu_get_default

Instead of searching the device tree every time, one static variable is declared for the default system x86 IOMMU device. Signed-off-by: Peter Xu --- hw/i386/acpi-build.c| 9 ++--- hw/i386/x86-iommu.c | 23 +++

[Qemu-devel] [PATCH v11 01/28] x86-iommu: introduce parent class

Introducing parent class for intel-iommu devices named "x86-iommu". This is preparation work to abstract shared functionalities out from Intel and AMD IOMMUs. Currently, only the parent class is introduced. It does nothing yet. Signed-off-by: Peter Xu ---

[Qemu-devel] [PATCH v11 02/28] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu

Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 11 +++ include/hw/i386/intel_iommu.h | 1 - include/hw/i386/x86-iommu.h | 2 ++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[Qemu-devel] [PATCH v11 00/28] IOMMU: Enable interrupt remapping for Intel IOMMU

This is v11 of Intel IR work. It is rebased to mst's branch "tags/for_upstream", commit: "278a2a2 vmw_pvscsi: remove unnecessary internal msi state flag" This series mainly fixed several issues in v10 review comments, fixed one bug with RHEL guests, added acked-by for Paolo, and a fresh new

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

On Tue, 07/05 09:58, Sascha Silbe wrote: > Dear Fam (or Zheng?), Hi Sascha, Zheng is the last name here. :) > > Fam Zheng writes: > > > This was the only exceptional module init function that does something > > else than a simple list of bdrv_register() calls, in all the

Re: [Qemu-devel] [RFC PATCH v0 1/5] cpu: Factor out cpu vmstate_[un]register into separate routines

On Tue, 5 Jul 2016 13:08:28 +0530 Bharata B Rao wrote: > On Tue, Jul 05, 2016 at 09:22:30AM +0200, Igor Mammedov wrote: > > On Tue, 5 Jul 2016 12:05:35 +0530 > > Bharata B Rao wrote: > > > > > On Tue, Jul 05, 2016 at 07:49:38AM +0200,

[Qemu-devel] [PATCH for-2.7 2/8] pc-bios/s390-ccw.img: rebuild image

Contains: - pc-bios/s390-ccw: Pass selected SCSI device to IPL Signed-off-by: Cornelia Huck --- pc-bios/s390-ccw.img | Bin 26424 -> 26440 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/pc-bios/s390-ccw.img b/pc-bios/s390-ccw.img index

Re: [Qemu-devel] [PATCH v2 0/3] seabios: add serial console support

On Mon, Jul 04, 2016 at 10:39:51PM +0200, Gerd Hoffmann wrote: > Hi, > > Next round of patches. Changes: > > * Moved it all to a new sercon.c file. > * Code maps cp437 to utf8 now, giving a much nicer display. Compare >"Use the ↑ and ↓ keys to change the selection." (this series) with

[Qemu-devel] [PATCH for-2.7 7/8] s390x/css: Factor out virtual css bridge and bus

From: Jing Liu Currently, common base layers virtual css bridge and bus are defined in hw/s390x/virtio-ccw.c(h). In order to support multiple types of devices in the virtual channel subsystem, especially non virtio-ccw, refactoring work needs to be done. This work is

[Qemu-devel] [PATCH for-2.7 8/8] s390x/css: Unplug handler of virtual css bridge

From: Jing Liu The previous patch moved virtual css bridge and bus out from virtio-ccw, but kept the direct reference of virtio-ccw specific unplug function inside css-bridge.c. To make the virtual css bus and bridge useful for non-virtio devices, this introduces a

[Qemu-devel] [PATCH for-2.7 6/8] s390x/css: use define for "virtual-css-bridge" literal

From: Sascha Silbe Introduce a TYPE_* define (like we already use for a couple of other QOM types) for the name of the virtual CSS bridge QOM type instead of sprinkling the same string literal over several source files. Signed-off-by: Sascha Silbe

Re: [Qemu-devel] [PATCH] quorum: Only compile when supported

Dear Fam (or Zheng?), Fam Zheng writes: > This was the only exceptional module init function that does something > else than a simple list of bdrv_register() calls, in all the block > drivers. > > The qcrypto_hash_supports is actually a static check, determined at > compile

[Qemu-devel] [PATCH for-2.7 4/8] s390x/ipl: fix reboots for migration from different bios

From: David Hildenbrand When migrating from a different QEMU version, the start_address and bios_start_address may differ. During migration these values are migrated and overwrite the values that were detected by QEMU itself. On a reboot, QEMU will reload its own BIOS,

[Qemu-devel] [PATCH for-2.7 1/8] pc-bios/s390-ccw: Pass selected SCSI device to IPL

From: "Eugene (jno) Dvurechenski" There is ,bootindex=%d argument to specify the lookup order of boot devices. If a bootindex assigned to the device, then IPL Parameter Info Block is created for that device when it is IPLed from. If it is a mere SCSI device (not FCP),

[Qemu-devel] [PATCH for-2.7 0/8] More s390x patches for 2.7

The following patches (and the s390x pci patches already on the list) make up the last batch of s390x patches I plan to do for 2.7 (except for bug fixes that may crop up, of course). We have several fixes/enhancements in the boot code and a bit of refactoring in the css code that makes the future

[Qemu-devel] [PATCH for-2.7 5/8] s390x/css: factor out some generic code from virtio_ccw_device_realize()

From: Sascha Silbe A lot of what virtio_ccw_device_realize() does isn't specific to virtio; it would apply to emulated CCW as well. Factor it out to make it easier to implement emulated CCW devices later on. Signed-off-by: Sascha Silbe

[Qemu-devel] [PATCH for-2.7 3/8] s390x/ipl: Support IPL from selected SCSI device

From: Alexander Yarygin If bootindex is specified for a device, we need to IPL from it. Currently it works for ccw devices, but not for SCSI. To be able to IPL from the specific device, pc-bios needs to know its address. For this reason we add special QEMU_SCSI IPL

Re: [Qemu-devel] [PATCH 1/2] linux-user: Add loop control ioctls

Le 04/07/2016 à 18:06, Peter Maydell a écrit : > Add support for the /dev/loop-control ioctls: > LOOP_CTL_ADD > LOOP_CTL_REMOVE > LOOP_CTL_GET_FREE > > Signed-off-by: Peter Maydell Reviewed-by: Laurent Vivier > --- > linux-user/ioctls.h

Re: [Qemu-devel] [PATCH v10 24/26] kvm-irqchip: do explicit commit when update irq

On Mon, Jul 04, 2016 at 04:23:32PM +0200, Paolo Bonzini wrote: > FWIW I prefer this to the "v10.2". Let me drop v10.2 then. Thanks, -- peterx

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