Hi
- Original Message -
> On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
>
> Grammar in subject is a bit terse; maybe:
>
> char: move QIOChannel-related stuff to char-io.h
>
> > Signed-off-by: Marc-André Lureau
> > ---
> > chardev/char-io.h | 24
On 01/13/2017 06:02 AM, Ladi Prosek wrote:
> The AHCI emulation code supports 64-bit addressing and should advertise this
> fact in the Host Capabilities register. Both Linux and Windows drivers test
> this bit to decide if the upper 32 bits of various registers may be written
> to, and at least
On 13 January 2017 at 17:27, Ard Biesheuvel wrote:
> Hi all,
>
> I tracked down a boot issue I was having with running the kernel under
> AArch64 system emulation to commit
>
59a71b4c5b4e target-arm: Use new deposit and extract ops
> It appears that ubfx is executing
On 01/13/2017 04:52 AM, Laurent Vivier wrote:
> +if (reg0 == 7 && opsize == OS_BYTE &&
> +m68k_feature(s->env, M68K_FEATURE_M68000)) {
> +tcg_gen_subi_i32(tmp, reg, 2);
> +} else {
> +tcg_gen_addi_i32(tmp, reg,
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char-win.h| 30 ++
> chardev/char-win.c| 242 +++
> chardev/char.c| 253
>
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Those could probably be squashed with earlier patches, however I
> couldn't easily identify them, test them or check if there are still
> necessary on various platforms.
>
> Signed-off-by: Marc-André Lureau
> ---
bdrv_refresh_filename() can do the same and it has some checks whether
the filename can actually be inherited or not, so we can let it do its
job in bdrv_open_inherit() after bdrv_open_common() has been called.
The only thing we need to set in bdrv_open_common() is the
exact_filename of a BDS
In places which directly pass a filename to the OS, we should not use
the filename field at all but exact_filename instead (although the
former currently equals the latter if that is set).
In raw_open_common(), we do not need to access BDS.filename because we
already have a local variable
If an event is dynamically disabled, the TCG code that calls the
execution-time tracer is not generated.
Removes the overheads of execution-time tracers for dynamically disabled
events. As a bonus, also avoids checking the event state when the
execution-time tracer is called from TCG-generated
Last patch removed a nesting level in generated code. Re-align all code
generated by backends to be 4-column aligned.
Signed-off-by: Lluís Vilanova
---
scripts/tracetool/backend/dtrace.py |4 ++--
scripts/tracetool/backend/ftrace.py | 20 ++--
*** This series is based on v4 of my ***
*** "block: Fix some filename generation issues" series ***
The BDS filename field is generally only used when opening disk images
or emitting error or warning messages, the only exception to this rule
is the map command of qemu-img. However, using
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char-parallel.h | 9 ++
> chardev/char-parallel.c | 293
>
> chardev/char.c | 288
The patch in 59a71b4c5b4e suffered from a merge failure
when compared to the original patch in
http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1
Paolo Bonzini writes:
> On 12/01/2017 20:37, Lluís Vilanova wrote:
>> Stefan Hajnoczi writes:
>>
>>> On Tue, Jan 10, 2017 at 05:31:37PM +0100, Paolo Bonzini wrote:
On 09/01/2017 18:01, Stefan Hajnoczi wrote:
> Or use a simpler scheme:
>
> struct CPUState {
> ...
>
On 01/13/2017 10:36 AM, Laurent Vivier wrote:
> On 680x0 family only.
>
> Address Register indirect With postincrement:
>
> When using the stack pointer (A7) with byte size data, the register
> is incremented by two.
>
> Address Register indirect With predecrement:
>
> When using the stack
Instead of returning a pointer to the filename, g_strdup() it. This will
become necessary once we do not have BlockDriverState.filename anymore.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
---
The optimizations of this series makes it feasible to have them
available on all builds.
Signed-off-by: Lluís Vilanova
---
trace-events |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/trace-events b/trace-events
index f74e1d3d22..0a0f4d9cd6
There were some patterns, like 0x___00ff, for which we
would select to begin a multi-insn sequence with MOVN, but would
fail to set the 0x lane back from 0x.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
Message-Id:
remote-tracking branch
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging (2017-01-13
14:38:21 +)
are available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-tcg-20170113
for you to fetch changes up to 8cf9a3d3f7a4b95f33e0bda5416b9c93ec887dd3
The function is reused in later patches.
Signed-off-by: Lluís Vilanova
Reviewed-by: Richard Henderson
---
cputlb.c|2 +-
include/exec/exec-all.h |6 ++
translate-all.c | 14 +-
3 files changed, 16
The variable was renamed s390_facilities.
Signed-off-by: Richard Henderson
---
tcg/s390/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 0682d01..a679280 100644
---
When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
Message-Id: <20161207180727.6286-2-...@twiddle.net>
---
tcg/aarch64/tcg-target.inc.c | 9
On 01/13/2017 02:01 PM, Ladi Prosek wrote:
> On Fri, Jan 13, 2017 at 7:31 PM, John Snow wrote:
>>
>>
>> On 01/13/2017 01:12 PM, Ladi Prosek wrote:
>>> On Fri, Jan 13, 2017 at 6:23 PM, John Snow wrote:
On 01/13/2017 06:02 AM, Ladi Prosek wrote:
> The
On 01/13/2017 10:44 AM, Markus Armbruster wrote:
> This is Marc-André's "[PATCH v8 00/21] qapi doc generation (whole
> version, squashed)" with a few commit messages tweaked, and "[PATCH v8
> 14/21] (SQUASHED) move doc to schema" unsquashed into 161 patches.
>
> We did all the respins with in
Every vCPU now uses a separate set of TBs for each set of dynamic
tracing event state values. Each set of TBs can be used by any number of
vCPUs to maximize TB reuse when vCPUs have the same tracing state.
This feature is later used by tracetool to optimize tracing of guest
code events.
The
Later patches will make use of it.
Signed-off-by: Lluís Vilanova
---
trace/control-internal.h |7 ++-
trace/control.c | 11 +++
trace/control.h |4 ++--
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git
*file should always be set (to NULL, if nothing else) instead of leaving
it dangling sometimes. This should also be documented so callers can
rely on this behavior.
Signed-off-by: Max Reitz
---
block/io.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Optimizes tracing of events with the 'tcg' and 'vcpu' properties (e.g., memory
accesses), making it feasible to statically enable them by default on all QEMU
builds.
Some quick'n'dirty numbers with 400.perlbench (SPECcpu2006) on the train input
(medium size - suns.pl) and the guest_mem_before
Split the part which actually refreshes the BlockDriverState.filename
field off of bdrv_refresh_filename() into a more generic function
bdrv_filename(), which first calls bdrv_refresh_filename() and then
stores a qemu-usable filename in the given buffer instead of
BlockDriverState.filename.
Since
This keeps consistency across all decisions taken during translation
when the dynamic state of a vCPU is changed in the middle of translating
some guest code.
Signed-off-by: Lluís Vilanova
---
include/qom/cpu.h |3 +++
qom/cpu.c |2 ++
On 13 January 2017 at 16:36, Ard Biesheuvel wrote:
> Linux for arm64 v4.10 and later will complain if the ECAM config space is
> not reserved in the ACPI namespace:
>
> acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x3f00-0x3fff] not
> reserved in ACPI
On 01/13/2017 04:51 AM, Laurent Vivier wrote:
> M680x0 bit operations with an immediate value use 9 bits of the 16bit
> value, while coldfire ones use only 8 bits.
I don't see that in the reference manual. Where do you get this from?
r~
* Peter Xu (pet...@redhat.com) wrote:
> Adding one more option "-f" for "info mtree" to dump the flat views of
> all the address spaces.
>
> This will be useful to debug the memory rendering logic, also it'll be
> much easier with it to know what memory region is handling what address
> range.
>
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 23e2b06..cf5d8dd 100644
--- a/target/m68k/translate.c
+++
On 680x0 family only.
Address Register indirect With postincrement:
When using the stack pointer (A7) with byte size data, the register
is incremented by two.
Address Register indirect With predecrement:
When using the stack pointer (A7) with byte size data, the register
is decremented by two.
On Fri, Jan 13, 2017 at 7:31 PM, John Snow wrote:
>
>
> On 01/13/2017 01:12 PM, Ladi Prosek wrote:
>> On Fri, Jan 13, 2017 at 6:23 PM, John Snow wrote:
>>> On 01/13/2017 06:02 AM, Ladi Prosek wrote:
The AHCI emulation code supports 64-bit addressing and
On Fri, Jan 13, 2017 at 6:23 PM, John Snow wrote:
> On 01/13/2017 06:02 AM, Ladi Prosek wrote:
>> The AHCI emulation code supports 64-bit addressing and should advertise this
>> fact in the Host Capabilities register. Both Linux and Windows drivers test
>> this bit to decide if
This is a series of fixes for target/m68k found:
- with RISU (bit operation with immediate)
- while debugging package build under chroot
(gen_flush_flags() and CAS address modes)
- while I was working on the softmmu mode
(CAS alignment and SP address modes)
v2:
- Don't align stack access on
In these cases we must update the address register after
the operation.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate.c
On Fri, Jan 13, 2017 at 03:09:46PM +, Felipe Franciosi wrote:
> Hi Marc-Andre,
>
> > On 13 Jan 2017, at 07:03, Marc-André Lureau wrote:
> >
> > Hi
> >
> > - Original Message -
> >> Currently, VQs are started as soon as a SET_VRING_KICK is received. That
> >> is
On Fri, Jan 13, 2017 at 01:17:27PM +, Stefan Hajnoczi wrote:
> On Fri, Jan 13, 2017 at 07:56:51PM +0800, Haozhong Zhang wrote:
> > The missing of 'nvdimm' in the machine type option '-M' means NVDIMM
> > is disabled. QEMU should refuse to plug any NVDIMM device in this case
> > and report the
When CPU vendor is set to AMD, the AMD feature alias bits on
CPUID[0x8001].EDX are already automatically copied from CPUID[1].EDX
on x86_cpu_realizefn(). When CPU vendor is Intel, those bits are
reserved and should be zero. On either case, those bits shouldn't be set
in the CPU model table.
This is Marc-André's "[PATCH v8 00/21] qapi doc generation (whole
version, squashed)" with a few commit messages tweaked, and "[PATCH v8
14/21] (SQUASHED) move doc to schema" unsquashed into 161 patches.
We did all the respins with in this squashed form to reduce noise.
However, since the
The server can handle MAX_REQ - 1 PDUs at a time and the virtio-9p
device has a MAX_REQ sized virtqueue. If the client manages to fill
up the virtqueue, pdu_alloc() will fail and the request won't be
processed without any notice to the client (it actually causes the
linux 9p client to hang).
This
On 01/13/2017 01:12 PM, Ladi Prosek wrote:
> On Fri, Jan 13, 2017 at 6:23 PM, John Snow wrote:
>> On 01/13/2017 06:02 AM, Ladi Prosek wrote:
>>> The AHCI emulation code supports 64-bit addressing and should advertise this
>>> fact in the Host Capabilities register. Both Linux
On Fri, Jan 13, 2017 at 09:06:52AM -0500, Jason J. Herne wrote:
> On 01/13/2017 05:04 AM, Jiri Denemark wrote:
> > On Thu, Jan 12, 2017 at 11:18:11 -0500, Collin L. Walling wrote:
> > > When running on s390 with a kernel that does not support cpu model
> > > checking and
> > > with a Qemu new
On 01/13/2017 04:52 AM, Laurent Vivier wrote:
> In these cases we must update the address register after
> the operation.
>
> Signed-off-by: Laurent Vivier
> ---
> target/m68k/translate.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Richard Henderson
On 12 January 2017 at 17:53, Eduardo Habkost wrote:
> The following changes since commit 204febd17f9ebb9e94b1980b42c7f2c2307851c1:
>
> libqtest: handle zero length memwrite/memread (2017-01-12 10:45:59 +)
>
> are available in the git repository at:
>
>
Hi all,
I tracked down a boot issue I was having with running the kernel under
AArch64 system emulation to commit
It appears that ubfx is executing incorrectly: the following code
.global _start
_start:
mov x1, #0x1124
ubfx x2, x1, #28, #4
built with
aarch64-linux-gnu-gcc -o
On 01/13/2017 09:27 AM, Ard Biesheuvel wrote:
> Hi all,
>
> I tracked down a boot issue I was having with running the kernel under
> AArch64 system emulation to commit
>
> It appears that ubfx is executing incorrectly: the following code
>
> .global _start
> _start:
> mov x1, #0x1124
>
Le 13/01/2017 à 18:55, Richard Henderson a écrit :
> On 01/13/2017 04:51 AM, Laurent Vivier wrote:
>> M680x0 bit operations with an immediate value use 9 bits of the 16bit
>> value, while coldfire ones use only 8 bits.
>
> I don't see that in the reference manual. Where do you get this from?
Linux for arm64 v4.10 and later will complain if the ECAM config space is
not reserved in the ACPI namespace:
acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x3f00-0x3fff] not
reserved in ACPI namespace
The rationale is that OSes that don't consume the MCFG table should still
be able
On 01/13/2017 04:52 AM, Laurent Vivier wrote:
> gen_flush_flags() is setting unconditionally cc_op_synced to 1
> and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
> to something else by a previous tcg fragment.
>
> We fix that by not setting cc_op_synced to 1
> (except for
On 01/13/2017 10:23 AM, Laurent Vivier wrote:
> See "BSET Instruction Format:BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE
> DATA", p. 4.58 of "M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL", "BIT
> NUMBER" is bits 0 to 8 of extended word.
Oops, yep. I misread that.
Reviewed-by: Richard Henderson
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.
Signed-off-by: Laurent Vivier
Reviewed-by: Richard Henderson
---
target/m68k/translate.c | 13 ++---
1 file changed, 10 insertions(+),
Marc-André Lureau writes:
> Hi
>
> - Original Message -
>> Marc-André Lureau writes:
>>
>> > Python code style accepts both form, but pep8 complains. Better to clean
>> > up the single warning for now, so new errors stand out more
> On 13 Jan 2017, at 09:04, Michael S. Tsirkin wrote:
>
> On Fri, Jan 13, 2017 at 03:09:46PM +, Felipe Franciosi wrote:
>> Hi Marc-Andre,
>>
>>> On 13 Jan 2017, at 07:03, Marc-André Lureau wrote:
>>>
>>> Hi
>>>
>>> - Original Message -
On 01/13/2017 04:52 AM, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> target/m68k/translate.c | 1 -
> 1 file changed, 1 deletion(-)
Huh. Wow. Ok.
Reviewed-by: Richard Henderson
r~
On Fri, Jan 13, 2017 at 05:15:22PM +, Felipe Franciosi wrote:
>
> > On 13 Jan 2017, at 09:04, Michael S. Tsirkin wrote:
> >
> > On Fri, Jan 13, 2017 at 03:09:46PM +, Felipe Franciosi wrote:
> >> Hi Marc-Andre,
> >>
> >>> On 13 Jan 2017, at 07:03, Marc-André Lureau
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.
We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)
FIX:
> On 13 Jan 2017, at 10:18, Michael S. Tsirkin wrote:
>
> On Fri, Jan 13, 2017 at 05:15:22PM +, Felipe Franciosi wrote:
>>
>>> On 13 Jan 2017, at 09:04, Michael S. Tsirkin wrote:
>>>
>>> On Fri, Jan 13, 2017 at 03:09:46PM +, Felipe Franciosi wrote:
>
> On Fri, Jan 13, 2017 at 02:54:29AM +, Gonglei (Arei) wrote:
> >
> > >
> > > On Thu, Jan 12, 2017 at 12:26:24PM +, Gonglei (Arei) wrote:
> > > > Hi,
> > > >
> > > >
> > > > >
> > > > > On 01/04/2017 11:10 AM, Gonglei (Arei) wrote:
> > > > > > Hi all,
> > > > > >
> > > > > > I attach
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Saturday, January 14, 2017 12:18 AM
> To: qemu-devel@nongnu.org
> Cc: Gonglei (Arei)
> Subject: [PATCH] virtio_crypto: header update
>
> Update header from latest linux driver. Session creation structs gain
Marc-André Lureau writes:
> Follow documentation guideline, body, parameters then additional
> sections.
>
> Signed-off-by: Marc-André Lureau
As proposed in review of v7, I'm replacing commit message by
qapi: Reorder doc comments for
Marc-André Lureau writes:
> Use a better 'Note:' section, move it below parameters following
> guidelines.
>
> Signed-off-by: Marc-André Lureau
As proposed in review of v7, I'm replacing commit message by
qapi: Move "command is
Update header from latest linux driver. Session creation structs gain
padding to make them same size. Formatting cleanups.
Signed-off-by: Michael S. Tsirkin
---
include/standard-headers/linux/virtio_crypto.h | 481 +
1 file changed, 251 insertions(+),
Marc-André Lureau writes:
> Python code style accepts both form, but pep8 complains. Better to clean
> up the single warning for now, so new errors stand out more easily.
>
> Fix scripts/qapi.py:1539:21: W503 line break before binary operator
>
> Signed-off-by:
In 4.10, Linux is switching from __bitwise__ to use __bitwise
exclusively. Update our script accordingly.
Signed-off-by: Michael S. Tsirkin
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh
Hi
- Original Message -
> Marc-André Lureau writes:
>
> > Python code style accepts both form, but pep8 complains. Better to clean
> > up the single warning for now, so new errors stand out more easily.
> >
> > Fix scripts/qapi.py:1539:21: W503 line break
On Fri, 13 Jan 2017 09:57:36 +1100
David Gibson wrote:
> On Thu, Jan 12, 2017 at 11:31:35AM +0100, Andrea Bolognani wrote:
> > On Mon, 2017-01-09 at 10:46 +1100, David Gibson wrote:
> > > > >* To allow for hotplugged devices, libvirt should also add a number
>
On Fri, Jan 13, 2017 at 10:45:09AM +0800, Jason Wang wrote:
>
>
> On 2017年01月12日 22:17, Michael S. Tsirkin wrote:
> > On Wed, Jan 11, 2017 at 12:32:12PM +0800, Jason Wang wrote:
> > > This patches implements Device IOTLB support for vhost kernel. This is
> > > done through:
> > >
> > > 1)
Linux for arm64 v4.10 and later will complain if the ECAM config space is
not reserved in the ACPI namespace:
acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x3f00-0x3fff] not
reserved in ACPI namespace
The rationale is that OSes that don't consume the MCFG table should still
be able
On 01/13/2017 12:48 PM, Lluís Vilanova wrote:
uring and controlling the state of tracing events.
*
- * Copyright (C) 2011-2016 Lluís Vilanova
+ * Copyright (C) 2011-2017 Lluís Vilanova
*
* This work is licensed under the terms of the GNU GPL,
On 01/13/2017 12:48 PM, Lluís Vilanova wrote:
This keeps consistency across all decisions taken during translation
when the dynamic state of a vCPU is changed in the middle of translating
some guest code.
Signed-off-by: Lluís Vilanova
---
include/qom/cpu.h |3 +++
On Fri, Jan 13, 2017 at 05:58:02PM +0200, Michael S. Tsirkin wrote:
> On Fri, Jan 13, 2017 at 11:06:26AM +0800, Peter Xu wrote:
> > v3:
> > - fix style error reported by patchew
> > - fix comment in domain switch patch: use "IOMMU address space" rather
> > than "IOMMU region" [Kevin]
> > - add
On 01/12/2017 03:46 AM, Stefan Hajnoczi wrote:
The virtio_queue_set_notification() nesting introduced for AioContext polling
raised an assertion with virtio-net (even in non-polling mode). Converting
virtio-net and virtio-crypto to use virtio_queue_set_notification() in a
nesting fashion would
I am working on testing instruction emulation patches for the linux
kernel. During testing I found these 2 issues:
- sets DSX (delay slot exception) but never clears it
- EEAR for illegal insns should point to the bad exception (as per
openrisc spec) but its not
This patch fixes these two
Greg Kurz writes:
> This may be used for deprecated object properties that are kept for
> backwards compatibility.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Markus Armbruster
Happy to merge this as soon as we have an actual user.
Have the TODO in the TAG: format, so they will stand out in the
generated documentation.
Signed-off-by: Marc-André Lureau
---
qapi-schema.json | 4 ++--
qapi/introspect.json | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/qapi-schema.json
TransactionAction is a flat union, document 'type' versions
exhaustively, and sort the members.
Signed-off-by: Marc-André Lureau
Reviewed-by: Markus Armbruster
---
qapi-schema.json | 31 ---
1 file changed, 16
'device_add' is still incomplete for now, but we can fix a few
arguments:
- 'bus' is a common argument, regardless of the device
- 'id' is an optional argument
Signed-off-by: Marc-André Lureau
Reviewed-by: Markus Armbruster
Reviewed-by: Eric Blake
Itemize the possible return values of guest-set-vcpus.
Drop the blank lines for consistency with itemized
lists elsewhere.
Signed-off-by: Marc-André Lureau
Reviewed-by: Markus Armbruster
---
qga/qapi-schema.json | 11 ---
1 file changed,
Add some more section titles to organize the documentation we're going
to generate.
Signed-off-by: Marc-André Lureau
Reviewed-by: Markus Armbruster
---
qapi-schema.json | 4
qapi/block-core.json | 6 --
qapi/block.json | 10
Following documentation guidelines.
Signed-off-by: Marc-André Lureau
---
qapi-schema.json | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/qapi-schema.json b/qapi-schema.json
index 1d4f27f1a3..bcbf72bf59 100644
--- a/qapi-schema.json
+++
Python code style accepts both form, but pep8 complains. Better to clean
up the single warning for now, so new errors stand out more easily.
Fix scripts/qapi.py:1539:21: W503 line break before binary operator
Signed-off-by: Marc-André Lureau
---
scripts/qapi.py | 4
Both the cpu->tb_jmp_cache and SoftMMU TLB structures are only used
when running TCG code so we might as well skip them for anything else.
Signed-off-by: Alex Bennée
Reviewed-by: Eduardo Habkost
---
qom/cpu.c | 10 ++
1 file changed, 6
On 12 January 2017 at 02:55, Richard Henderson wrote:
> Mark Cave-Ayland asked me to handle the merge of this patch set
> while he is traveling.
>
> This is the v2 that Artyom posted today. I had reviewed the majority
> of v1 earlier. I re-read through the rebase and saw
On Fri, Jan 13, 2017 at 09:53:31AM +0800, He Chen wrote:
> AVX512_VPOPCNTDQ: Vector POPCNT instructions for word and qwords.
> variable precision.
>
> Signed-off-by: He Chen
Reviewed-by: Eduardo Habkost
Applied to x86-next. Thanks!
--
Eduardo
On 12 January 2017 at 13:16, Alex Bennée wrote:
> The following changes since commit b44486dfb9447c88e4b216e730adcc780190852c:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20170110-1' into
> staging (2017-01-10 14:52:34 +)
>
> are available in the
Learn a few more markups used for API documentation.
Signed-off-by: Marc-André Lureau
---
scripts/texi2pod.pl | 54 ++---
1 file changed, 51 insertions(+), 3 deletions(-)
diff --git a/scripts/texi2pod.pl
Replace with '*', the common form for list items.
Signed-off-by: Marc-André Lureau
---
qapi-schema.json | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qapi-schema.json b/qapi-schema.json
index eab8d4a9ee..1d4f27f1a3 100644
---
Follow documentation guideline, body, parameters then additional
sections.
Signed-off-by: Marc-André Lureau
---
qapi-schema.json | 10 +-
qapi/event.json | 4 ++--
qapi/introspect.json | 3 +--
3 files changed, 8 insertions(+), 9 deletions(-)
Add a qapi2texi script to generate the documentation from the qapi
schemas.
The SQUASHED patch in this series is a squashed version of the
documentation move from qmp-commands.txt to the schemas. The whole
version (not sent on the ML to avoid spamming) is in the following git
branch:
Use a better 'Note:' section, move it below parameters following
guidelines.
Signed-off-by: Marc-André Lureau
---
qapi/block-core.json | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/qapi/block-core.json
ECB mode cipher doesn't need IV, if we setiv for it then qemu
crypto API would report "Expected IV size 0 not **", so we should
setiv only when the cipher algos really need.
Signed-off-by: Longpeng(Mike)
---
backends/cryptodev-builtin.c | 10 ++
1 file changed, 6
Sometimes it is useful to have just a machine with CPU and RAM, without
any further hardware in it, e.g. if you just want to do some instruction
debugging for TCG with a remote GDB attached to QEMU, or run some embedded
code with the "-semihosting" QEMU parameter. qemu-system-m68k already
features
On 13 January 2017 at 03:37, Amit Shah wrote:
> On (Fri) 06 Jan 2017 [12:10:22], Peter Maydell wrote:
>> On 5 January 2017 at 16:32, Amit Shah wrote:
>> > The following changes since commit
>> > dbe2b65566e76d3c3a0c3358285c0336ac61e757:
>> >
>> >
Cc: Stefan Weil
Cc: Samuel Thibault
Signed-off-by: Gerd Hoffmann
---
ui/sdl2.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 9a79b17..91fb111 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -817,9
On 01/13/2017 08:12 AM, Cao jin wrote:
> Also move certain hunk above, to place msix init related code together.
>
> CC: Hannes Reinecke
> CC: Paolo Bonzini
> CC: Markus Armbruster
> CC: Marcel Apfelbaum
> CC: Michael S.
On 01/13/2017 04:22 PM, Markus Armbruster wrote:
> Cao jin writes:
>
>> Only a tiny modification in patch "megasas: remove unnecessary
>> megasas_use_msix()" to fix a megasas issue.
>
> Please have a look at Michael's review in
> Message-ID:
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