In v7M, the fixed-priority exceptions are:
Reset: -3
NMI: -2
HardFault: -1
In v8M, this changes because Secure HardFault may need
to be prioritised above NMI:
Reset: -4
Secure HardFault if AIRCR.BFHFNMINS == 1: -3
NMI: -2
Secure HardFault if AIRCR.BFHFNMINS == 0: -1
NonSecure HardFault:
QTAILQ_FOREACH_SAFE() must be used when removing the current element
inside the loop block.
This fixes a user-after-free error introduced by commit 56258174238eb
and reported by Coverity (CID 1381017).
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_events.c |4 ++--
1 file
Ok. It looks like EDK was added to my distro and using it fixed it -
https://packages.gentoo.org/packages/sys-firmware/edk2-ovmf (at least
W16 - I'll try W10 tonight).
Unfortunately when I run strings on edk I haven't seen anything which
looked like version.
--
You received this bug
Resending. It did not reach virtio-dev the first time.
On Tue, 12 Sep 2017 16:29:47 +0200
Tomáš Golembiovský wrote:
> On Tue, 29 Aug 2017 20:01:53 +0800
> Wei Wang wrote:
>
> > On 08/29/2017 05:57 PM, Stefan Hajnoczi wrote:
> > > On Sun, Aug 27, 2017
On 09/12/2017 04:37 PM, Cornelia Huck wrote:
> On Mon, 11 Sep 2017 13:36:29 +0200
> Halil Pasic wrote:
>
>> On 09/11/2017 12:07 PM, Cornelia Huck wrote:
>>> On Fri, 8 Sep 2017 17:24:46 +0200
>>> Halil Pasic wrote:
>>>
We report
Fix an error that meant we were wiring every UART's overflow
interrupts into the same inputs 0 and 1 of the OR gate,
rather than giving each its own input.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
---
hw/arm/mps2.c | 4 ++--
1 file changed, 2
On Tue, Sep 12, 2017 at 05:52:18PM +0200, Paolo Bonzini wrote:
> On 12/09/2017 12:46, Daniel P. Berrange wrote:
> > Currently before submitting a series, devs should run checkpatch.pl
> > across each patch to be submitted. This can be automated using a
> > command such as:
> >
> > git rebase -i
* David Gibson (da...@gibson.dropbear.id.au) wrote:
> On Mon, Sep 11, 2017 at 10:30:33AM +0100, Dr. David Alan Gilbert wrote:
> > * Greg Kurz (gr...@kaod.org) wrote:
> > > On Sun, 10 Sep 2017 15:37:33 +0100
> > > Mark Cave-Ayland wrote:
> > >
> > > > Commit a90db15
On Tue, Sep 12, 2017 at 06:14:57PM +0200, Paolo Bonzini wrote:
> On 12/09/2017 18:12, Daniel P. Berrange wrote:
> > On Tue, Sep 12, 2017 at 05:52:18PM +0200, Paolo Bonzini wrote:
> >> On 12/09/2017 12:46, Daniel P. Berrange wrote:
> >>> Currently before submitting a series, devs should run
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 2 +
tcg/tcg.c | 310 ++
2 files changed, 312
Nothing uses or implements them yet.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg-opc.h | 89 +++
Nothing uses or enables them yet.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 5 +
tcg/tcg.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
Add with value 0 so that structure zero initialization can
indicate that the field is not present.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg-opc.h | 2 ++
There was a problem here with an ILP32 host with 64 host registers.
E.g. aarch64 running in ILP32 mode.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index
Signed-off-by: Richard Henderson
---
tcg/tcg.h| 1 -
tcg/aarch64/tcg-target.inc.c | 2 +-
tcg/arm/tcg-target.inc.c | 2 +-
tcg/i386/tcg-target.inc.c| 4 ++--
tcg/mips/tcg-target.inc.c| 2 +-
tcg/ppc/tcg-target.inc.c | 2 +-
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 1 -
tcg/tcg.c | 8
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 7226727ee4..e168bd2c44 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -210,7 +210,6 @@ typedef enum
Hi Paolo,
Hmm did you just resend your v1? Except the cover the patches don't have
"v2" and I remember reviewing this one (also Eric Blake replied with his
R-b).
On 09/12/2017 11:44 AM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
tests/qemu-iotests/check
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 23 ++-
tcg/aarch64/tcg-target.inc.c | 372 ++-
2 files changed, 350 insertions(+), 45 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h
It's not even clear what the interface REG and VAL32 were supposed to mean.
All uses had REG = 0 and VAL32 was the bitset assigned to the destination.
Signed-off-by: Richard Henderson
---
tcg/tcg.h| 1 -
tcg/aarch64/tcg-target.inc.c | 33
On Tue, Sep 12, 2017 at 3:53 AM, Igor Mammedov wrote:
> On Tue, 5 Sep 2017 19:12:26 -0300
> Eduardo Habkost wrote:
>
>> On Tue, Sep 05, 2017 at 02:47:52PM -0700, Alistair Francis wrote:
>> > On Tue, Sep 5, 2017 at 2:31 PM, Eduardo Habkost
On 12 September 2017 at 17:22, Philippe Mathieu-Daudé wrote:
> (CC'ed qemu-arm)
>
> Hi Peter,
>
> On 09/12/2017 01:13 PM, Peter Maydell wrote:
>>
>> Fix an error that meant we were wiring every UART's overflow
>> interrupts into the same inputs 0 and 1 of the OR gate,
>> rather
On 12/09/2017 18:30, Philippe Mathieu-Daudé wrote:
> Hi Paolo,
>
> Hmm did you just resend your v1? Except the cover the patches don't have
> "v2" and I remember reviewing this one (also Eric Blake replied with his
> R-b).
I didn't include the R-bs, sorry (most of the later patches had
On 09/12/2017 09:12 AM, Laurent Desnogues wrote:
>> +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
>> +{
>> +tcg_clear_temp_count();
>> +}
>
> Is it really needed to call tcg_clear_temp_count here when it's now
> called in translator_loop?
Nope, missed while moving
Kevin,
thanks again. You've provided enough support for me at this point. I had
looked at trying to coalesce multiple -drive values into a single one, and that
can definitely be made to work with the newer qemu, but i'm not sure I can make
it work with older.
the goal there would be to do
On 08/23/2017 01:19 PM, Marc-André Lureau wrote:
This simplify a little bit memory management in the following patches.
Signed-off-by: Marc-André Lureau
---
contrib/vhost-user-scsi/vhost-user-scsi.c | 18 +-
1 file changed, 9 insertions(+), 9
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v2 00/16] TCG vectorization and example conversion
Message-id: 20170912162513.21694-1-richard.hender...@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On 12/09/17 17:21, Dr. David Alan Gilbert wrote:
>> Right, a subsection is certainly necessary to avoid breaking backwards
>> migration.
>>
>> But apart from that I want to understand better exactly why this is
>> necessary. What's the state that's being lost, and is it really not
>> recoverable
On 08/23/2017 01:19 PM, Marc-André Lureau wrote:
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
contrib/vhost-user-scsi/vhost-user-scsi.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 12/09/17 17:41, Mark Cave-Ayland wrote:
> The commit message mentions that prior to the conversion some CPU state
> was missing but it doesn't mention anything about dropping existing
> fields as part of the conversion process so I suspect that this was an
> accidental side-effect.
Actually
On 08/23/2017 01:19 PM, Marc-André Lureau wrote:
There is no need to include hw/virtio/virtio-scsi.h, then the conflict
with SCSI_XFER enum goes away.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
On 08/23/2017 01:20 PM, Marc-André Lureau wrote:
And actually link to it from vhost-user-bridge.
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
Makefile | 3 ++-
tests/Makefile.include | 2 +-
2
Currently before submitting a series, devs should run checkpatch.pl
across each patch to be submitted. This can be automated using a
command such as:
git rebase -i master -x 'git show | ./scripts/checkpatch.pl -'
This is rather long winded to type, so this patch introduces a way
to tell
On 09/11/2017 01:49 PM, Philippe Mathieu-Daudé wrote:
> -atomic_set((uint64_t *)jmp_addr, pair);
> +atomic_set__nocheck((uint64_t *)jmp_addr, pair);
> flush_icache_range(jmp_addr, jmp_addr + 8);
> } else {
> intptr_t diff = addr - jmp_addr;
>
Queued,
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
preempt execution. The simple way to achieve this is to clear the
enable bit for it, since the enable bit isn't guest visible.
Signed-off-by: Peter Maydell
Instead of looking up the pending priority
in nvic_pending_prio(), cache it in a new state struct
field. The calculation of the pending priority given
the interrupt number is more complicated in v8M with
the security extension, so the caching will be worthwhile.
This changes nvic_pending_prio()
Handle banking of SHCSR: some register bits are banked between
Secure and Non-Secure, and some are only accessible to Secure.
Signed-off-by: Peter Maydell
---
hw/intc/armv7m_nvic.c | 221 ++
1 file changed, 169
Make the set_prio() function take a bool indicating
whether to pend the secure or non-secure version of a banked
interrupt, and use this to implement the correct banking
semantics for the SHPR registers.
Signed-off-by: Peter Maydell
---
hw/intc/armv7m_nvic.c | 96
Update nvic_exec_prio() to support the v8M changes:
* BASEPRI, FAULTMASK and PRIMASK are all banked
* AIRCR.PRIS can affect NS priorities
* AIRCR.BFHFNMINS affects FAULTMASK behaviour
These changes mean that it's no longer possible to
definitely say that if FAULTMASK is set it overrides
Now that we have adjusted the majority of the calls this function
makes to be byte-based, it is easier to read the code if it makes
passes over the image using bytes rather than sectors.
Signed-off-by: Eric Blake
Reviewed-by: John Snow
Reviewed-by: Vladimir
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> tests/qemu-iotests/check | 4 ++--
> tests/qemu-iotests/common| 2 +-
> tests/qemu-iotests/common.config | 3 ---
> 3 files changed, 3 insertions(+), 6 deletions(-)
Both callers already had bytes available, but were scaling to
sectors. Move the scaling to internal code. In the case of
bdrv_aligned_pwritev(), we are now passing the exact offset
rather than a rounded sector-aligned value, but that's okay
as long as dirty bitmap widens start/bytes to
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> This includes shell function, shell variables and command line options
> (randomize.awk does not exist).
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/qemu-iotests/check | 28 -
>
- float64 regs[64];
+ float64 regs[64] __attribute__((aligned(16)));
I understand this should be aligned to the biggest vector register the
host support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it
correct?
checking datashits:
"INTEL® ADVANCED VECTOR EXTENSIONS"
On 09/12/2017 02:01 PM, Richard Henderson wrote:
On 09/11/2017 01:49 PM, Philippe Mathieu-Daudé wrote:
-atomic_set((uint64_t *)jmp_addr, pair);
+atomic_set__nocheck((uint64_t *)jmp_addr, pair);
flush_icache_range(jmp_addr, jmp_addr + 8);
} else {
This series adds an API to add instrumentation events.
It also provides additional APIs for:
* Controlling tracing events.
* Peek/poke guest memory.
TODO:
* Replace qi_event_gen_* with generating calls to arbitrary functions (e.g.,
qi_event_gen_call(num_args, va_list)).
* Flush all TBs when an
On 11/09/2017 21:52, Alistair Francis wrote:
> This series expands on my previous series by converting more existing
> prints to use warn_report() instead of error_report() or fprintf().
>
> As discussed with Paolo and Markus this series combines libqemustub.a into
> libqemuutil.a to avoid
On 11/09/2017 23:37, Peter Maydell wrote:
> On 11 September 2017 at 21:49, Philippe Mathieu-Daudé wrote:
>> this fixes building for ppc64 on ppc32 (changed in 5964fca8a12c):
>>
>> qemu/tcg/ppc/tcg-target.inc.c: In function 'tb_target_set_jmp_target':
>>
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> Some functions in common.rc are never used by the tests. Move
> them out of that file and into common, which is already included
> only by "check".
>
> Code that actually *is* common to "check" and tests can be placed in
> common.config.
>
>
Signed-off-by: Lluís Vilanova
---
MAINTAINERS |6 ++
docs/instrument.txt | 173 +++
2 files changed, 179 insertions(+)
create mode 100644 docs/instrument.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index
Signed-off-by: Lluís Vilanova
---
configure |9 +
1 file changed, 9 insertions(+)
diff --git a/configure b/configure
index fd7e3a5e81..a21d1bceb9 100755
--- a/configure
+++ b/configure
@@ -356,6 +356,7 @@ pie=""
qom_cast_debug="yes"
trace_backends="log"
Public bug reported:
We recently discovered that file(1) fails on qemu-sh4-user when running
on an ELF file:
(sid_sh4)root@vs94:/# file /bin/bash
/bin/bash: ERROR: ELF 32-bit LSB executable, Renesas SH, version 1 (SYSV) error
reading (Invalid argument)
(sid_sh4)root@vs94:/#
Running with "-d"
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> Instead of ./check failing when a binary is missing, we try each test
> case now and each one fails with tons of test case diffs. Also, all the
> variables were initialized by "check" prior to "common" being sourced,
> and then (uselessly) checked
Signed-off-by: Lluís Vilanova
---
MAINTAINERS |1
Makefile.objs|4 +
configure|3 +
instrument/Makefile.objs |4 +
instrument/cmdline.c | 128 +++
instrument/cmdline.h | 51
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> These are never used by "check", with one exception that does not need
> $QEMU_OPTIONS. Keep them in common.rc, which will be soon included only
> by the tests.
>
> Signed-off-by: Paolo Bonzini
> ---
>
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> It only provides functions used by the test programs.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/qemu-iotests/check | 6 --
> tests/qemu-iotests/common.rc | 13 +
> 2 files changed, 5 insertions(+), 14
Signed-off-by: Lluís Vilanova
---
linux-user/main.c| 21 +
linux-user/syscall.c |4
2 files changed, 25 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 03666ef657..ac5c30c1fb 100644
--- a/linux-user/main.c
+++
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: 20170911213328.9701-5-f4...@amsat.org
accel/tcg/tcg-runtime.c | 54 -
accel/tcg/user-exec.c | 52
Signed-off-by: Lluís Vilanova
---
bsd-user/main.c| 17 +
bsd-user/syscall.c |5 +
2 files changed, 22 insertions(+)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 8a6706a1c8..104844edfc 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> Split "check" parts from tests part.
>
> For the directory setup, the actual computation of directories goes
> in "check", while the sanity checks go in the tests.
>
> Signed-off-by: Paolo Bonzini
> ---
>
Signed-off-by: Lluís Vilanova
---
qemu-options.hx | 19 +++
vl.c| 15 +++
2 files changed, 34 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 9f6e2adfff..6947388aab 100644
--- a/qemu-options.hx
+++
On 09/12/2017 03:55 PM, Peter Maydell wrote:
I notice we have a QEMU_ALIGNED() macro to wrap the __attribute__,
though we use it less often than not at the moment...
Aesthetic aside, I find it useful to deal with the 80 characters style
limit.
On 12 September 2017 at 21:17, Philippe Mathieu-Daudé wrote:
> On 09/12/2017 03:55 PM, Peter Maydell wrote:
>>
>> I notice we have a QEMU_ALIGNED() macro to wrap the __attribute__,
>> though we use it less often than not at the moment...
>
>
> Aesthetic aside, I find it useful to
When subdividing a bitmap serialization, the code in hbitmap.c
enforces that start/count parameters are aligned (except that
count can end early at end-of-bitmap). We exposed this required
alignment through bdrv_dirty_bitmap_serialization_align(), but
forgot to actually check that we comply with
There are patches floating around to add NBD_CMD_BLOCK_STATUS,
but NBD wants to report status on byte granularity (even if the
reporting will probably be naturally aligned to sectors or even
much higher levels). I've therefore started the task of
converting our block status code to report at a
All callers of bdrv_img_create() pass in a size, or -1 to read the
size from the backing file. We then set that size as the QemuOpt
default, which means we will reuse that default rather than the
final parameter to qemu_opt_get_size() several lines later. But
it is rather confusing to read
The only client of hbitmap_serialization_granularity() is dirty-bitmap's
bdrv_dirty_bitmap_serialization_align(). Keeping the two names consistent
is worthwhile, and the shorter name is more representative of what the
function returns (the required alignment to be used for start/count of
other
We had several functions that no one is currently using, and which
use sector-based interfaces. I'm trying to convert towards byte-based
interfaces, so it's easier to just drop the unused functions:
bdrv_dirty_bitmap_get_meta
bdrv_dirty_bitmap_get_meta_locked
bdrv_dirty_bitmap_reset_meta
We've previously fixed several places where we failed to account
for possible errors from bdrv_nb_sectors(). Fix another one by
making bdrv_dirty_bitmap_truncate() report the error rather then
silently resizing bitmaps to -1. Then adjust the sole caller
bdrv_truncate() to both reduce the
We're already reporting bytes for bdrv_dirty_bitmap_granularity();
mixing bytes and sectors in our return values is a recipe for
confusion. A later cleanup will convert dirty bitmap internals
to be entirely byte-based, but in the meantime, we should report
the bitmap size in bytes.
The only
Half the callers were already scaling bytes to sectors; the other
half can eventually be simplified to use byte iteration. Both
callers were already using the result as a bool, so make that
explicit. Making the change also makes it easier for a future
dirty-bitmap patch to offload scaling over
Right now, the dirty-bitmap code exposes the fact that we use
a scale of sector granularity in the underlying hbitmap to anything
that wants to serialize a dirty bitmap. It's nicer to uniformly
expose bytes as our dirty-bitmap interface, matching the previous
change to bitmap size. The only
We are gradually converting to byte-based interfaces, as they are
easier to reason about than sector-based. Change the qcow2 bitmap
helper function sectors_covered_by_bitmap_cluster(), renaming it
to bytes_covered_by_bitmap_cluster() in the process.
Signed-off-by: Eric Blake
We are still using an internal hbitmap that tracks a size in sectors,
with the granularity scaled down accordingly, because it lets us
use a shortcut for our iterators which are currently sector-based.
But there's no reason we can't track the dirty bitmap size in bytes,
since it is (mostly) an
Now that we have adjusted the majority of the calls this function
makes to be byte-based, it is easier to read the code if it makes
passes over the image using bytes rather than sectors.
Signed-off-by: Eric Blake
Reviewed-by: John Snow
Reviewed-by: Vladimir
All callers to bdrv_dirty_iter_new() passed 0 for their initial
starting point, drop that parameter.
Most callers to bdrv_set_dirty_iter() were scaling a byte offset to
a sector number; the exception qcow2-bitmap will be converted later
to use byte rather than sector iteration. Move the scaling
Thanks to recent cleanups, most callers were scaling a return value
of sectors into bytes (the exception, in qcow2-bitmap, will be
converted to byte-based iteration later). Update the interface to
do the scaling internally instead.
In qcow2-bitmap, the code was specifically checking for an error
Thanks to recent cleanups, all callers were scaling a return value
of sectors into bytes; do the scaling internally instead.
Signed-off-by: Eric Blake
---
v7: fix one more trace caller [Kevin]
v4-v6: no change
v3: no change, add R-b
v2: no change
---
block/dirty-bitmap.c |
Now that all callers are using byte-based interfaces, there's no
reason for our internal hbitmap to remain with sector-based
granularity. It also simplifies our internal scaling, since we
already know that hbitmap widens requests out to granularity
boundaries.
Signed-off-by: Eric Blake
Some of the callers were already scaling bytes to sectors; others
can be easily converted to pass byte offsets, all in our shift
towards a consistent byte interface everywhere. Making the change
will also make it easier to write the hold-out callers to use byte
rather than sectors for their
This is new code, but it is easier to read if it makes passes over
the image using bytes rather than sectors (and will get easier in
the future when bdrv_get_block_status is converted to byte-based).
Signed-off-by: Eric Blake
Reviewed-by: John Snow
---
v7:
Now that we have adjusted the majority of the calls this function
makes to be byte-based, it is easier to read the code if it makes
passes over the image using bytes rather than sectors.
Signed-off-by: Eric Blake
Reviewed-by: John Snow
---
v6: no change
v5:
On Mon, Sep 11, 2017 at 01:06:23PM +0200, Marc-André Lureau wrote:
> It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X.
>
> Signed-off-by: Marc-André Lureau
Reviewed-by: Eduardo Habkost
--
Eduardo
On Mon, Sep 11, 2017 at 05:06:00PM +0200, Igor Mammedov wrote:
> On Mon, 11 Sep 2017 16:31:39 +0200
> Thomas Huth wrote:
>
> > On 11.09.2017 14:53, Igor Mammedov wrote:
> > > On Thu, 7 Sep 2017 11:22:42 +0200
> > > Thomas Huth wrote:
> > >
> > >>
Possibly a duplicate of:
https://bugs.launchpad.net/qemu/+bug/1714331
or
https://bugs.launchpad.net/qemu/+bug/1715700
Can you share with us the version of OVMF you are using and potentially
try a newer version (see lp 1714331) If not, keep your eye on lp 1715700
for updates.
--
You received
For the v8M security extension, some exceptions must be banked
between security states. Add the new vecinfo array which holds
the state for the banked exceptions and migrate it if the
CPU the NVIC is attached to implements the security extension.
Signed-off-by: Peter Maydell
This patchset is another lump of v8M support. It mostly
covers the NVIC, which has extensive changes to handle the
fact that some exceptions are now banked. It sits on top of
the set of minor fixes that I sent out the other day.
(I have a chunk of patches that follow on from this to add
the
For v8M, the NVIC has a new set of registers per interrupt,
NVIC_ITNS. These determine whether the interrupt targets Secure
or Non-secure state. Implement the register read/write code for
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for
Update the code in nvic_rettobase() so that it checks the
sec_vectors[] array as well as the vectors[] array if needed.
Signed-off-by: Peter Maydell
---
hw/intc/armv7m_nvic.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c
Now that we have a banked FAULTMASK register and banked exceptions,
we can implement the correct check in cpu_mmu_index() for whether
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
handlers which have requested a negative execution priority to run
with the MPU disabled. In v8M
On 09/11/2017 02:33 PM, Philippe Mathieu-Daudé wrote:
>
> Philippe Mathieu-Daudé (4):
> tcg: move user-exec
> tcg: move tcg-runtime to accel/tcg/
> tcg: move atomic_template.h to accel/tcg/
> tcg: restrict i386 regs definitions
>
> Thomas Huth (1):
> tcg: Move softmmu_template.h to the
Update the nvic_recompute_state() code to handle the security
extension and its associated banked registers.
Code that uses the resulting cached state (ie the irq
acknowledge and complete code) will be updated in a later
commit.
Signed-off-by: Peter Maydell
---
In armv7m_nvic_set_pending() we have to compare the
priority of an exception against the execution priority
to decide whether it needs to be escalated to HardFault.
In the specification this is a comparison against the
exception's group priority; for v7M we implemented it
as a comparison against
On Tue, 12 Sep 2017 18:28:04 +0100
Peter Maydell wrote:
> On 8 September 2017 at 11:35, David Gibson
> wrote:
> > From: Daniel Henrique Barboza
> >
> > The sPAPR machine isn't clearing up the pending events
On 09/12/2017 01:25 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg.h| 1 -
tcg/aarch64/tcg-target.inc.c | 2 +-
tcg/arm/tcg-target.inc.c | 2 +-
On 09/12/2017 01:25 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg.h | 1 -
tcg/tcg.c | 8
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg.h
On 09/12/2017 01:25 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tcg/tcg.h | 4
tcg/tcg.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/tcg/tcg.h
On 09/08/2017 09:04 AM, Eric Blake wrote:
>>> void bdrv_dirty_bitmap_truncate(BlockDriverState *bs)
>>> {
>>> BdrvDirtyBitmap *bitmap;
>>> -uint64_t size = bdrv_nb_sectors(bs);
>>> +int64_t size = bdrv_getlength(bs);
>>>
>>> +assert(size >= 0);
>>
>> How can you assert that
> > +then
> > +if [ -x "$build_iotests/qemu" ]; then
> > +export QEMU_PROG="$build_iotests/qemu"
> > +elif [ -x "$build_root/$arch-softmmu/qemu-system-$arch" ]; then
> > +export QEMU_PROG="$build_root/$arch-softmmu/qemu-system-$arch"
> > +else
> > +pushd
On 09/12/2017 09:44 AM, Paolo Bonzini wrote:
> The variable is used in "common" but defined only after the file
> is sourced.
>
> Signed-off-by: Paolo Bonzini
> ---
> tests/qemu-iotests/check | 2 --
> tests/qemu-iotests/common | 2 ++
> 2 files changed, 2 insertions(+), 2
Signed-off-by: Lluís Vilanova
---
MAINTAINERS |1 +
Makefile |1 +
instrument/Makefile.objs |1 +
instrument/qmp.c | 82 ++
monitor.c|4 ++
qapi-schema.json
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