Re: [Qemu-devel] QEMU virt board: extending various limits

(adding Ard, Igor, Wei, Leif) On 01/16/18 16:07, Peter Maydell wrote: > We've had discussions before about the various limits in the virt > board imposed by its current address space layout: > * number of CPUs limited to 123 (not enough space for more redistributors) > * number of PCIe devices

Re: [Qemu-devel] [PATCH v2 1/4] linux-user: Move CPU type name selection to a function

On 01/16/2018 02:25 PM, Laurent Vivier wrote: > Instead of a sequence of "#if ... #endif" move the > selection to a function in linux-user/*/target_elf.h > > We can't add them in linux-user/*/target_cpu.h > because we will need to include "elf.h" to > use ELF flags with eflags, and including >

Re: [Qemu-devel] [PATCH v2 2/4] acpi: build QEMU table for PPI virtual memory device

On 01/16/18 16:51, Stefan Berger wrote: > To avoid having to hard code the base address of the PPI virtual memory > device we introduce a QEMU ACPI table that holds the base address, if a > TPM 1.2 or 2 is used. This table gives us flexibility to move the base > address later on. > >

Re: [Qemu-devel] [PATCH v2 11/32] qcow2: Remove BDS parameter from qcow2_cache_is_table_offset()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to pass it > to qcow2_cache_get_table_addr(). This is no longer necessary so this > parameter can be removed. > > Signed-off-by: Alberto Garcia > --- >

[Qemu-devel] [PATCH v3 1/4] linux-user: Move CPU type name selection to a function

Instead of a sequence of "#if ... #endif" move the selection to a function in linux-user/*/target_elf.h We can't add them in linux-user/*/target_cpu.h because we will need to include "elf.h" to use ELF flags with eflags, and including "elf.h" in "target_cpu.h" introduces some conflicts in

[Qemu-devel] [PATCH v3 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

From: YunQiang Su So here we need to detect the version of binaries and set cpu_model for it. [lv: original patch modified to move code into cpu_get_model()] Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson ---

Re: [Qemu-devel] [PATCH v2 17/32] qcow2: Update get_cluster_table() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This patch updates get_cluster_table() to return L2 slices instead of > full L2 tables. > > The code itself needs almost no changes, it only needs to call > offset_to_l2_slice_index() instead of offset_to_l2_index(). This patch > also renames all

Re: [Qemu-devel] [PATCH v2 18/32] qcow2: Update qcow2_get_cluster_offset() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > qcow2_get_cluster_offset() checks how many contiguous bytes are > available at a given offset. The returned number of bytes is limited > by the amount that can be addressed without having to load more than > one L2 table. > > Since we'll be loading

Re: [Qemu-devel] [PATCH v2 07/32] qcow2: Remove BDS parameter from qcow2_cache_put()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to pass it > to qcow2_cache_get_table_idx(). This is no longer necessary so this > parameter can be removed. > > Signed-off-by: Alberto Garcia > --- >

[Qemu-devel] [PATCH v3 0/4] linux-user: select CPU type according ELF header values

This idea has been suggested to me before by Philippe Mathieu-Daudé, and recently YunQiang Su has proposed a patch to manage the MIPS r6 case. Based on this, this series tries to clean-up the original patch, and introduces the use for m68k architecture and port the patch from YunQiang Su. v3:

[Qemu-devel] [PATCH v3 3/4] linux-user, m68k: select CPU according to ELF header values

M680x0 doesn't support the same set of instructions as ColdFire, so we can't use "any" CPU type to execute m68020 instructions. We select CPU type ("m68040" or "any" for ColdFire) according to the ELF header. If we can't, we use by default the value used until now: "any". Signed-off-by: Laurent

Re: [Qemu-devel] [PATCH x86-next v2] target-i386: add PCID flag to Westmere, Sandy Bridge and Ivy Bridge

On Tue, Jan 16, 2018 at 05:43:44PM +, Daniel P. Berrange wrote: > On Tue, Jan 16, 2018 at 03:08:15PM -0200, Eduardo Habkost wrote: > > [CCing Daniel] [...] > > I still don't understand why OpenStack doesn't let users add or > > modify elements on the domain XML. This isn't the first time I

Re: [Qemu-devel] [PULL v1 0/8] Xilinx queue

On Tue, Jan 16, 2018 at 6:54 AM, Peter Maydell wrote: > On 16 January 2018 at 14:49, Edgar E. Iglesias > wrote: >> This didn't show up on my clang testing, do you mind sharing configure line >> and clang version you use? >> >> @Alistair, it

Re: [Qemu-devel] [PATCH v6 11/21] hw/arm/xilinx_zynq: implement SDHCI Spec v2

On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/arm/xilinx_zynq.c | 64 >

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On 17/01/18 09:34, David Gibson wrote: > On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: >> On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: Correct me if I'm wrong, but it seems to me like there's no way to figure out through QMP whether these new machine options

[Qemu-devel] [PATCH v5 0/9] Add the ZynqMP PMU and IPI

This series adds the ZynqMP Power Management Unit (PMU) machine with basic functionality. The machine only has the - CPU - Memory - Interrupt controller - IPI device connected, but that is enough to run some of the ROM and firmware code on the machine The series also adds the IPI device

Re: [Qemu-devel] [PATCH v6 4/9] block: treat BDRV_REQ_ALLOCATE as serialising

On 01/16/2018 07:04 AM, Anton Nefedov wrote: > The idea is that ALLOCATE requests may overlap with other requests. > Reuse the existing block layer infrastructure for serialising requests. > Use the following approach: > - mark ALLOCATE serialising, so subsequent requests to the area wait > -

Re: [Qemu-devel] [PATCH v2 2/4] acpi: build QEMU table for PPI virtual memory device

On 01/16/2018 03:42 PM, Laszlo Ersek wrote: On 01/16/18 16:51, Stefan Berger wrote: To avoid having to hard code the base address of the PPI virtual memory device we introduce a QEMU ACPI table that holds the base address, if a TPM 1.2 or 2 is used. This table gives us flexibility to move the

Re: [Qemu-devel] [PATCH v2 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

Le 16/01/2018 à 21:29, Philippe Mathieu-Daudé a écrit : > On 01/16/2018 02:25 PM, Laurent Vivier wrote: >> From: YunQiang Su >> >> So here we need to detect the version of binaries and set >> cpu_model for it. >> >> [lv: original patch modified to move code into cpu_get_model()]

Re: [Qemu-devel] [PATCH v2 16/32] qcow2: Update l2_allocate() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This patch updates l2_allocate() to support the qcow2 cache returning > L2 slices instead of full L2 tables. > > The old code simply gets an L2 table from the cache and initializes it > with zeroes or with the contents of an existing table. With a

Re: [Qemu-devel] [PATCH v2 22/32] qcow2: Update discard_single_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > discard_single_l2() limits the number of clusters to be discarded to > the amount that fits inside an L2 table. Since we'll be loading L2 > slices instead of full tables we need to update that limit. > > Apart from that, this function doesn't need

[Qemu-devel] [PATCH v5 5/9] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller

Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- default-configs/microblaze-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 +

[Qemu-devel] [PATCH v5 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU

Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- V4: - Move the IPI to the machine instead of the SoC hw/microblaze/xlnx-zynqmp-pmu.c | 31 +++ 1 file changed, 31 insertions(+) diff --git

Re: [Qemu-devel] [PATCH v2 3/4] linux-user, m68k: select CPU according to ELF header values

On 01/16/2018 09:25 AM, Laurent Vivier wrote: > M680x0 doesn't support the same set of instructions > as ColdFire, so we can't use "any" CPU type to execute > m68020 instructions. > We select CPU type ("m68020" or "any" for ColdFire) > according to the ELF header. If we can't, we > use by default

Re: [Qemu-devel] [PATCH v2 12/32] qcow2: Add offset_to_l1_index()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Similar to offset_to_l2_index(), this function returns the index in > the L1 table for a given guest offset. This is only used in a couple > of places and it's not a particularly complex calculation, but it > makes the code a bit more readable. > >

Re: [Qemu-devel] [PATCH v2 31/32] qcow2: Allow configuring the L2 slice size

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Now that the code is ready to handle L2 slices we can finally add an > option to allow configuring their size. > > An L2 slice is the portion of an L2 table that is read by the qcow2 > cache. Until now the cache was always reading full L2 tables,

[Qemu-devel] [PATCH v5 2/9] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due

[Qemu-devel] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer

Previously if no device tree was passed to microblaze_load_kernel() then qemu_find_file() would try to find a NULL pointer. To avoid this put a check around qemu_find_file(). Signed-off-by: Alistair Francis Reported-by: Peter Maydell ---

Re: [Qemu-devel] [RFC PATCH 02/10] block/qapi: Add qcow2 create options to schema

On 01/16/2018 02:11 PM, Kevin Wolf wrote: >>> +{ 'enum': 'BlockdevQcow2CompatLevel', >>> + 'data': [ '0_10', '1_1' ] } >> >> Enums are allowed to start with digits while struct members are not; so >> you can get away with this naming. Do we really want the names 0_10 and >> 1_1, or are there

Re: [Qemu-devel] [PATCH v2 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

On 01/16/2018 09:25 AM, Laurent Vivier wrote: > From: YunQiang Su > > So here we need to detect the version of binaries and set > cpu_model for it. > > [lv: original patch modified to move code into cpu_get_model()] > Signed-off-by: Laurent Vivier > ---

Re: [Qemu-devel] [PATCH v2] file-posix: specify expected filetypes

On 01/15/2018 04:50 PM, John Snow wrote: > I don't think there's a legitimate reason to open directories as if > they were files. This prevents QEMU from opening and attempting to probe > a directory inode, which can break in exciting ways. One of those ways > is lseek on ext4/xfs, which will

Re: [Qemu-devel] [PATCH qemu 0/3] spapr/iommu: Enable in-kernel TCE acceleration via VFIO KVM device

On Mon, 15 Jan 2018 15:12:07 +1100 Alexey Kardashevskiy wrote: > On 03/01/18 04:51, Paolo Bonzini wrote: > > On 02/01/2018 06:28, Alexey Kardashevskiy wrote: > >> This is my current queue of the in-kernel TCE acceleration > >> enablement. > >> > >> Changes since > >>

Re: [Qemu-devel] [PATCH v6 9/9] iotest 134: test cluster-misaligned encrypted write

On 01/16/2018 07:04 AM, Anton Nefedov wrote: > COW (even empty/zero) areas require encryption too > > Signed-off-by: Anton Nefedov > --- > tests/qemu-iotests/134 | 9 + > tests/qemu-iotests/134.out | 10 ++ > 2 files changed, 19 insertions(+)

Re: [Qemu-devel] [PATCH v2 05/32] qcow2: Remove BDS parameter from qcow2_cache_table_release()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to get the > cache table size (since it was equal to the cluster size). This is no > longer necessary so this parameter can be removed. > > Signed-off-by: Alberto Garcia

Re: [Qemu-devel] [PATCH v2 08/32] qcow2: Remove BDS parameter from qcow2_cache_destroy()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was never using the BlockDriverState parameter so it can > be safely removed. > > Signed-off-by: Alberto Garcia > --- > block/qcow2-cache.c | 2 +- > block/qcow2.c | 16 > block/qcow2.h

Re: [Qemu-devel] [PATCH v2 13/32] qcow2: Add l2_slice_size field to BDRVQcow2State

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > The BDRVQcow2State structure contains an l2_size field, which stores > the number of 64-bit entries in an L2 table. > > For efficiency reasons we want to be able to load slices instead of > full L2 tables, so we need to know how many entries an L2

Re: [Qemu-devel] [PATCH v2 19/32] qcow2: Update qcow2_alloc_cluster_link_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > There's a loop in this function that iterates over the L2 entries in a > table, so now we need to assert that it remains within the limits of > an L2 slice. > > Apart from that, this function doesn't need any additional changes, so > this patch

[Qemu-devel] [PATCH v5 7/9] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/intc/Makefile.objs | 1 + hw/intc/xlnx-zynqmp-ipi.c | 377

Re: [Qemu-devel] [PATCH v2 1/3] xlnx-zynqmp-rtc: Initial commit

On Mon, Jan 15, 2018 at 5:25 AM, Peter Maydell wrote: > On 12 January 2018 at 22:36, Alistair Francis > wrote: >> Initial commit of the ZynqMP RTC device. >> >> Signed-off-by: Alistair Francis >> --- >> V2: >>

[Qemu-devel] [PATCH v3 2/4] linux-user: introduce functions to detect CPU type

From: YunQiang Su Add a function to return ELF e_flags and use it to select the CPU model. [lv: split the patch and some cleanup in get_elf_eflags()] Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- Notes:

Re: [Qemu-devel] [PATCH v2 24/32] qcow2: Update qcow2_update_snapshot_refcount() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > qcow2_update_snapshot_refcount() increases the refcount of all > clusters of a given snapshot. In order to do that it needs to load all > its L2 tables and iterate over their entries. Since we'll be loading > L2 slices instead of full tables we need

Re: [Qemu-devel] [PATCH v2 26/32] qcow2: Update qcow2_truncate() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > The qcow2_truncate() code is mostly independent from whether > we're using L2 slices or full L2 tables, but in full and > falloc preallocation modes new L2 tables are allocated using > qcow2_alloc_cluster_link_l2(). Therefore the code needs to be >

Re: [Qemu-devel] [PATCH v6 20/21] sdhci: implement UHS-I voltage switch

On Thu, Jan 11, 2018 at 12:56 PM, Philippe Mathieu-Daudé wrote: > [based on a patch from Alistair Francis > from qemu/xilinx tag xilinx-v2015.2] > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis

Re: [Qemu-devel] [PATCH v2 02/32] qcow2: Add table size field to Qcow2Cache

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > The table size in the qcow2 cache is currently equal to the cluster > size. This doesn't allow us to use the cache memory efficiently, > particularly with large cluster sizes, so we need to be able to have > smaller cache tables that are independent

Re: [Qemu-devel] [PATCH v2 06/32] qcow2: Remove BDS parameter from qcow2_cache_entry_mark_dirty()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to pass it > to qcow2_cache_get_table_idx(). This is no longer necessary so this > parameter can be removed. > > Signed-off-by: Alberto Garcia > --- >

Re: [Qemu-devel] [PATCH v2 09/32] qcow2: Remove BDS parameter from qcow2_cache_clean_unused()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to pass it > to qcow2_cache_table_release(). This is no longer necessary so this > parameter can be removed. > > Signed-off-by: Alberto Garcia > --- >

Re: [Qemu-devel] [PATCH v2 15/32] qcow2: Update l2_load() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Each entry in the qcow2 L2 cache stores a full L2 table (which uses a > complete cluster in the qcow2 image). A cluster is usually too large > to be used efficiently as the size for a cache entry, so we want to > decouple both values by allowing

Re: [Qemu-devel] [PATCH v2 21/32] qcow2: Update handle_alloc() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > handle_alloc() loads an L2 table and limits the number of checked > clusters to the amount that fits inside that table. Since we'll be > loading L2 slices instead of full tables we need to update that limit. > > Apart from that, this function

Re: [Qemu-devel] [PATCH v5 0/9] Add the ZynqMP PMU and IPI

On Tue, Jan 16, 2018 at 3:22 PM, Alistair Francis wrote: > > This series adds the ZynqMP Power Management Unit (PMU) machine with basic > functionality. > > The machine only has the > - CPU > - Memory > - Interrupt controller > - IPI device > > connected, but that

[Qemu-devel] [PATCH] Add ability to provide ifname when using netdev bridge or tap helper

This patch replaces the patch I sent yesturday. This one fixes a bug in my original code as well as corrects a few styling issues. Hopfully this one comes out correct! Sorry for the inconvienece. When currently using -netdev bridge or -netdev tap with a helper you are unable to set an ifname.

Re: [Qemu-devel] [PATCH v2 6/8] docker: add the Fedora 27 base image

On 01/15/2018 01:38 PM, Philippe Mathieu-Daudé wrote: > On 01/15/2018 01:27 PM, Daniel P. Berrange wrote: >> On Mon, Jan 15, 2018 at 11:34:57AM -0300, Philippe Mathieu-Daudé wrote: >>> straight copy on Fedora 25 base. >>> >>> Suggested-by: Paolo Bonzini >>> Signed-off-by:

Re: [Qemu-devel] QEMU virt board: extending various limits

On 16 January 2018 at 20:18, Laszlo Ersek wrote: > (adding Ard, Igor, Wei, Leif) > > On 01/16/18 16:07, Peter Maydell wrote: >> We've had discussions before about the various limits in the virt >> board imposed by its current address space layout: >> * number of CPUs limited

Re: [Qemu-devel] [PATCH v2 01/32] qcow2: Fix documentation of get_cluster_table()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function has not been returning the offset of the L2 table since > commit 3948d1d4876065160583e79533bf604481063833 > > Signed-off-by: Alberto Garcia > --- > block/qcow2-cluster.c | 3 +-- > 1 file changed, 1 insertion(+), 2

Re: [Qemu-devel] [PATCH v2 10/32] qcow2: Remove BDS parameter from qcow2_cache_discard()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to pass it > to qcow2_cache_get_table_idx() and qcow2_cache_table_release(). This > is no longer necessary so this parameter can be removed. > > Signed-off-by: Alberto Garcia

Re: [Qemu-devel] [PATCH v2 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

Le 16/01/2018 à 21:26, Richard Henderson a écrit : > On 01/16/2018 09:25 AM, Laurent Vivier wrote: >> From: YunQiang Su >> >> So here we need to detect the version of binaries and set >> cpu_model for it. >> >> [lv: original patch modified to move code into cpu_get_model()] >>

Re: [Qemu-devel] [PATCH v2 14/32] qcow2: Add offset_to_l2_slice_index()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > Similar to offset_to_l2_index(), this function takes a guest offset > and returns the index in the L2 slice that contains its L2 entry. > > An L2 slice has currently the same size as an L2 table (one cluster), > so both functions return the same

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On 17/01/18 10:30, David Gibson wrote: > On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: >> On 17/01/18 09:34, David Gibson wrote: >>> On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: >> Correct

Re: [Qemu-devel] [PATCH] LEON3 IRQMP: Fix IRQ software ack

On Mon, Jan 15, 2018 at 9:27 AM, Jean-Christophe Dubois wrote: > Le 2018-01-15 14:45, Jean-Christophe Dubois a écrit : >> >> Le 2018-01-15 12:09, Fabien Chouteau a écrit : >>> >>> On 12/01/2018 15:10, Jean-Christophe Dubois wrote: Le 2018-01-12 11:55, Fabien

Re: [Qemu-devel] [PATCH] memory: update comments and fix some typos

Hi Paolo, Maybe it is a little boring to review updated comments, but I think it is the right thing to do, so could you have a look when you're free? Regards, Jay > -Original Message- > From: Zhoujian (jay) > Sent: Thursday, January 04, 2018 1:30 PM > To: qemu-devel@nongnu.org > Cc:

Re: [Qemu-devel] [PATCH v6 0/3] vhost: two fixes and used_memslots refactoring

> -Original Message- > From: Michael S. Tsirkin [mailto:m...@redhat.com] > Sent: Tuesday, January 16, 2018 12:42 PM > To: Zhoujian (jay) > Cc: qemu-devel@nongnu.org; imamm...@redhat.com; Huangweidong (C) > ; wangxin (U)

Re: [Qemu-devel] [PULL 00/25] pc, pci, virtio: features, fixes, cleanups

> On 16 Jan 2018, at 8:28, Jason Wang wrote: > > > > On 2018年01月16日 10:48, Michael S. Tsirkin wrote: >> On Tue, Jan 09, 2018 at 12:10:10PM +1100, David Gibson wrote: >>> On Mon, Jan 08, 2018 at 08:10:23PM +0200, Michael S. Tsirkin wrote: On Mon, Jan 08, 2018 at

Re: [Qemu-devel] qcow2 autoloading bitmaps

16.01.2018 00:26, John Snow wrote: On 01/11/2018 10:15 AM, Vladimir Sementsov-Ogievskiy wrote: 11.01.2018 17:43, Eric Blake wrote: On 01/11/2018 08:26 AM, Vladimir Sementsov-Ogievskiy wrote: # @autoload: the bitmap will be automatically loaded when the image it is stored #    in is

Re: [Qemu-devel] RFE for patchew docker result reporting

On Tue, Jan 16, 2018 at 10:16:28AM +0800, Fam Zheng wrote: > On Mon, Jan 15, 2018 at 8:26 PM, Cornelia Huck wrote: > > On Mon, 15 Jan 2018 11:48:41 + > > "Daniel P. Berrange" wrote: > > > >> Currently if I look at the patchew website for build logs,

Re: [Qemu-devel] [Qemu-arm] [PATCH] hw/misc: Add code to emulate Xilinx Slave Serial port

On 16 January 2018 at 05:04, Philippe Mathieu-Daudé wrote: > If devices have qtests for code coverage, I think we should accept them > upstream, even if they are not yet plugged into a board. > > The other way, there are motivated contributors who start sending > patches but then

Re: [Qemu-devel] [RFC PATCH 00/10] x-blockdev-create for qcow2

Am 11.01.2018 um 20:52 hat Kevin Wolf geschrieben: > This series implements a minimal QMP command that allows to create an > image format on a given block node. The interface is still going to > change to some kind of an async command (possibly a block job), so I > prefixed x- for now. > > At

[Qemu-devel] [PULL v1 3/8] aarch64-softmmu.mak: Use an ARM specific config

From: Alistair Francis In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options. Signed-off-by: Alistair Francis Acked-by: Peter Maydell

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

Hi On Tue, Jan 16, 2018 at 12:25 PM, Peter Maydell wrote: > On 15 January 2018 at 23:35, Paolo Bonzini wrote: >> The following changes since commit 997eba28a3ed5400a80f754bf3a1c8044b75b9ff: >> >> Merge remote-tracking branch >>

Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations

On 16 January 2018 at 03:33, Richard Henderson wrote: > I think this will be the last revision before queueing for pull. > > Peter, the target/arm patches here are primarily for testing, > without having to go all the way through to SVE. It also shows > how the

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/8] s390-ccw: update libc

On 01/15/2018 06:23 PM, Collin L. Walling wrote: > On 01/15/2018 12:05 PM, Eric Blake wrote: >> On 01/15/2018 10:44 AM, Collin L. Walling wrote: >>> Moved: >>>    memcmp from bootmap.h to libc.h (renamed from _memcmp) >>>    strlen from sclp.c to libc.h (renamed from _strlen) >>> >>> Added C

Re: [Qemu-devel] [PATCH 0/4] coroutine-lock: polymorphic CoQueue

On 01/16/2018 06:08 AM, Paolo Bonzini wrote: There are cases in which a queued coroutine must be restarted from non-coroutine context (with qemu_co_enter_next). In this cases, qemu_co_enter_next also needs to be thread-safe, but it cannot use a CoMutex and so cannot qemu_co_queue_wait. This

Re: [Qemu-devel] [PATCH v3 1/8] s390-ccw: update libc

On 15.01.2018 18:23, Collin L. Walling wrote: > On 01/15/2018 12:05 PM, Eric Blake wrote: >> On 01/15/2018 10:44 AM, Collin L. Walling wrote: [...] >>> +/** >>> + * atoi: >>> + * @str: the string to be converted. >>> + * >>> + * Given a string @str, convert it to an integer. Any non-numerical >>>

Re: [Qemu-devel] [PATCH v2 12/20] fpu/softfloat: re-factor mul

Peter Maydell writes: > On 9 January 2018 at 12:22, Alex Bennée wrote: >> We can now add float16_mul and use the common decompose and >> canonicalize functions to have a single implementation for >> float16/32/64 versions. >> >> Signed-off-by:

Re: [Qemu-devel] [PATCH] LEON3 IRQMP: Fix IRQ software ack

On 15/01/2018 18:27, Jean-Christophe Dubois wrote: > Le 2018-01-15 14:45, Jean-Christophe Dubois a écrit : >> >> Note: For now I am not so much interested in the AMBA discovery as the >> type of software platform I am thinking about is embedded where the >> hardware is well known ahead of time.

Re: [Qemu-devel] [PATCHv2 1/2] spapr: Allow some cases where we can't set VSMT mode in the kernel

On 16/01/2018 05:47, David Gibson wrote: > At present if we require a vsmt mode that's not equal to the kernel's > default, and the kernel doesn't let us change it (e.g. because it's an old > kernel without support) then we always fail. > > But in fact we can cope with the kernel having a

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

On 15 January 2018 at 23:35, Paolo Bonzini wrote: > The following changes since commit 997eba28a3ed5400a80f754bf3a1c8044b75b9ff: > > Merge remote-tracking branch > 'remotes/pmaydell/tags/pull-target-arm-20180111' into staging (2018-01-11 > 14:34:41 +) > > are

[Qemu-devel] [PULL v1 2/8] xlnx-zynqmp-pmu: Add the CPU and memory

From: Alistair Francis Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH RESEND v1 1/2] i386: Add Intel Processor Trace feature support

On Tue, Jan 16, 2018 at 06:10:17AM +, Kang, Luwei wrote: > > > On Mon, Jan 15, 2018 at 12:04:55 -0200, Eduardo Habkost wrote: > > > > CCing libvirt developers. > > > ... > > > > This case is slightly more problematic, however: the new feature is > > > > actually migratable (under very

[Qemu-devel] [PULL v1 7/8] xlnx-zynqmp-pmu: Connect the IPI device to the PMU

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias --- hw/microblaze/xlnx-zynqmp-pmu.c | 31

Re: [Qemu-devel] [PATCH] xilinx_spips: Correct usage of an uninitialized local variable

On 14 January 2018 at 22:55, Francisco Iglesias wrote: > Coverity found that the variable tx_rx in the function > xilinx_spips_flush_txfifo was being used uninitialized (CID 1383841). This > patch corrects this by always initializing tx_rx to zeros. > > Signed-off-by:

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

On 16 January 2018 at 11:58, Marc-André Lureau wrote: > Hi > > On Tue, Jan 16, 2018 at 12:25 PM, Peter Maydell > wrote: >> On 15 January 2018 at 23:35, Paolo Bonzini wrote: >>> The following changes since commit

Re: [Qemu-devel] [PATCH] LEON3 IRQMP: Fix IRQ software ack

On 15/01/2018 19:16, Mark Cave-Ayland wrote: > On 11/01/18 11:48, Fabien Chouteau wrote: > >> On 10/01/2018 21:43, Jean-Christophe Dubois wrote: >>> With the LEON3 IRQ controller IRQs can be acknoledged 2 ways: >>> * Explicitely by software writing to the CLEAR_OFFSET register >>> * Implicitely

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/2] Clean up the ppc default configs

On 16 January 2018 at 10:41, Thomas Huth wrote: > On 15.01.2018 13:00, BALATON Zoltan wrote: > [...] >> I've also noticed that most of the boards were available both in ppcemb >> and ppc targets so maybe these could be merged now to avoid confusion >> but I don't know the reason

Re: [Qemu-devel] [PATCH 1/4] lockable: add QemuLockable

On 01/16/2018 06:08 AM, Paolo Bonzini wrote: QemuLockable is a polymorphic lock type that takes an object and knows which function to use for locking and unlocking. The implementation could use C11 _Generic, but since the support is not very widespread I am instead using __builtin_choose_expr

Re: [Qemu-devel] [PATCH v2 1/4] tcg/arm: Fix double-word comparisons

On 16 January 2018 at 03:45, Richard Henderson wrote: > The code sequence we were generating was only good for unsigned > comparisons. For signed comparisions, use the sequence from gcc. > > Fixes booting of ppc64 firmware, with a patch changing the code > sequence

Re: [Qemu-devel] RFE for patchew docker result reporting

On Mon, Jan 15, 2018 at 8:26 PM, Cornelia Huck wrote: > On Mon, 15 Jan 2018 11:48:41 + > "Daniel P. Berrange" wrote: > >> Currently if I look at the patchew website for build logs, the 'docker' >> job results are listed as a single expandable item. >>

[Qemu-devel] [PULL v1 6/8] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

From: Alistair Francis This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH v8 00/14] SDHCI: housekeeping (part 1)

On 15 January 2018 at 18:24, Philippe Mathieu-Daudé wrote: > Since v7: > - addressed Peter & Paolo reviews > - do not use qdev_property_add_static() but move common properties into > a new DEFINE_SDHCI_COMMON_PROPERTIES() > - use _space_memory rather than create AS with

[Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

The threshold size is changed to be recorded in s->threshold_size by commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. Signed-off-by: Wei Wang --- migration/migration.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/migration/migration.c

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/2] Clean up the ppc default configs

On 16.01.2018 11:51, Peter Maydell wrote: > On 16 January 2018 at 10:41, Thomas Huth wrote: >> On 15.01.2018 13:00, BALATON Zoltan wrote: >> [...] >>> I've also noticed that most of the boards were available both in ppcemb >>> and ppc targets so maybe these could be merged now

[Qemu-devel] [PATCH 1/1] Add ifname support to -netdev tap and bridge when using helper

Hi, I've modified the qemu source to add support for specifying a ifname when using -netdev tap or -netdev bridge with a helper. Currently this is not supported and all interface names are named tap0, tap1, ... Hopfully i'm submitting this correctly, if not I appologize. Also, my C is a bit

Re: [Qemu-devel] [PATCH v2 07/20] fpu/softfloat: propagate signalling NaNs in MINMAX

Alex Bennée writes: > Peter Maydell writes: > >> On 9 January 2018 at 12:22, Alex Bennée wrote: >>> While a comparison between a QNaN and a number will return the number >>> it is not the same with a signaling NaN. In

Re: [Qemu-devel] [PATCHv2 1/2] spapr: Allow some cases where we can't set VSMT mode in the kernel

On Tue, 16 Jan 2018 15:47:13 +1100 David Gibson wrote: > At present if we require a vsmt mode that's not equal to the kernel's > default, and the kernel doesn't let us change it (e.g. because it's an old > kernel without support) then we always fail. > > But in fact

[Qemu-devel] [PATCH RFC] target-arm:Add a dynamic XML-description of the cp-registers to GDB

[PATCH RFC] target-arm:Add a dynamic XML-description of the cp-registers to GDB This patch offers to GDB the ability to read/write all the coprocessor registers for ARM and ARM64 by generating dynamically an XML-description for these registers. - gdbstub.c :         *Extend the

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/2] Clean up the ppc default configs

On 15.01.2018 13:00, BALATON Zoltan wrote: [...] > I've also noticed that most of the boards were available both in ppcemb > and ppc targets so maybe these could be merged now to avoid confusion > but I don't know the reason why ppcemb existed in the first place so I > don't know what other

Re: [Qemu-devel] [PATCH v2 07/20] fpu/softfloat: propagate signalling NaNs in MINMAX

Peter Maydell writes: > On 9 January 2018 at 12:22, Alex Bennée wrote: >> While a comparison between a QNaN and a number will return the number >> it is not the same with a signaling NaN. In this case the SNaN will >> "win" and after

[Qemu-devel] Help regarding configuring qemu with '--enable-ptnetmap' option

Hello, I am trying to configure qemu with ptnet. But it seems like, now there is no 'ptnet' branch to checkout, so I am unable to configure using '--enable-ptnetmap' option. please help in this regard. Thank you.

[Qemu-devel] [PULL v1 4/8] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller

From: Alistair Francis Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias ---

[Qemu-devel] [PULL v1 1/8] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

From: Alistair Francis The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU

[Qemu-devel] [PULL v1 0/8] Xilinx queue

From: "Edgar E. Iglesias" The following changes since commit f5213bd060b460c99e605472b7e03967db43: Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +) are available in the git repository at:

Re: [Qemu-devel] [PATCH v3 0/4] cryptodev: add vhost support

On Tue, Jan 16, 2018 at 02:21:32PM +, Zhoujian (jay) wrote: > VHOST_USER_CREATE_CRYPTO_SESSION and VHOST_USER_CLOSE_CRYPTO_SESSION are new > added messages, they should be sent only when > VHOST_USER_PROTOCOL_F_CRYPTO_SESSION feature has been successfully negotiated. > > The differs between

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