Re: [Qemu-devel] [PATCH v3 1/4] cryptodev: add vhost-user as a new cryptodev backend

On Tue, Jan 16, 2018 at 10:06:50PM +0800, Jay Zhou wrote: > From: Gonglei > > Usage: > -chardev socket,id=charcrypto0,path=/path/to/your/socket > -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 > -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0

[Qemu-devel] [PULL v2 4/4] tcg/ppc: Allow a 32-bit offset to the constant pool

We recently relaxed the limit of the number of opcodes that can appear in a TranslationBlock. In certain cases this has resulted in relocation overflow. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 67

Re: [Qemu-devel] [PATCH v5 3/7] vhost: Simplify ring verification checks

* Igor Mammedov (imamm...@redhat.com) wrote: > On Mon, 18 Dec 2017 20:13:36 + > "Dr. David Alan Gilbert (git)" wrote: > > > From: "Dr. David Alan Gilbert" > > > > vhost_verify_ring_mappings() were used to verify that > > rings are still accessible

[Qemu-devel] [PULL v2 0/4] tcg queued patches

With comments addressed from v1. r~ The following changes since commit aae39d24a387a273deab3eb930dbf730aa379e22: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180116' into staging (2018-01-16 14:18:20 +) are available in the Git repository at: git

Re: [Qemu-devel] [PATCH 05/11] virtio-ccw: convert VirtIOCCWDeviceClass::init -> realize

On Tue, 16 Jan 2018 10:15:49 -0300 Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/s390x/virtio-ccw.h | 2 +- > hw/s390x/virtio-ccw.c | 35 +-- > 2 files changed, 18 insertions(+), 19

Re: [Qemu-devel] [PATCH v4 11/14] ARM: Add basic code to emulate A7MPCore DAP block

On 01/16/2018 12:04 PM, Andrey Smirnov wrote: > On Mon, Jan 15, 2018 at 8:32 PM, Philippe Mathieu-Daudé > wrote: >> Hi Andrey, >> >> On 01/15/2018 10:37 PM, Andrey Smirnov wrote: >>> Add minimal code to emulate A7MPCore DAP block needed to boot Linux >>> guest. >> >> I was not

Re: [Qemu-devel] [PATCH v2 25/32] qcow2: Update expand_zero_clusters_in_l1() to support L2 slices

On 15/12/2017 3:53 PM, Alberto Garcia wrote: diff --git a/block/qcow2-cluster.c b/block/qcow2-cluster.c index 8f7a04ba7d..ab840a449f 100644 --- a/block/qcow2-cluster.c +++ b/block/qcow2-cluster.c [..] @@ -1907,124 +1911,133 @@ static int expand_zero_clusters_in_l1(BlockDriverState *bs,

Re: [Qemu-devel] [PATCH 1/3] linux-user: introduce functions to detect CPU type

Le 16/01/2018 à 16:54, Richard Henderson a écrit : > On 01/16/2018 06:13 AM, Laurent Vivier wrote: >>> There is no reason to read the elf header twice -- e_flags has already been >>> stored in the struct image_info. >> >> When we set cpu_model, image_info is not initialized. >> Do you propose to

Re: [Qemu-devel] [PATCH v2 31/32] qcow2: Allow configuring the L2 slice size

On 15/12/2017 3:53 PM, Alberto Garcia wrote: diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c index 2fcecbd7a8..fe58d1ec70 100644 --- a/block/qcow2-cache.c +++ b/block/qcow2-cache.c [..] @@ -879,9 +896,13 @@ static int qcow2_update_options_prepare(BlockDriverState *bs, }

Re: [Qemu-devel] [PATCH v2 2/4] acpi: build QEMU table for PPI virtual memory device

On Tue, Jan 16, 2018 at 10:51:38AM -0500, Stefan Berger wrote: > To avoid having to hard code the base address of the PPI virtual memory > device we introduce a QEMU ACPI table that holds the base address, if a > TPM 1.2 or 2 is used. This table gives us flexibility to move the base > address

[Qemu-devel] [PULL v2 1/4] tcg/arm: Fix double-word comparisons

The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth Reviewed-by: Peter

[Qemu-devel] [PULL v2 2/4] tcg/arm: Support tlb offsets larger than 64k

AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 30 +- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c

[Qemu-devel] [PULL v2 3/4] tcg/ppc: Support tlb offsets larger than 64k

AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index

Re: [Qemu-devel] [PATCH v2 16/32] qcow2: Update l2_allocate() to support L2 slices

On 15/12/2017 3:53 PM, Alberto Garcia wrote: This patch updates l2_allocate() to support the qcow2 cache returning L2 slices instead of full L2 tables. The old code simply gets an L2 table from the cache and initializes it with zeroes or with the contents of an existing table. With a cache

Re: [Qemu-devel] [PATCH v2 16/20] fpu/softfloat: re-factor float to int/uint

Alex Bennée writes: > We share the common int64/uint64_pack_decomposed function across all > the helpers and simply limit the final result depending on the final > size. > > Signed-off-by: Alex Bennée > > -- > v2 > - apply float_flg_invalid

Re: [Qemu-devel] [RFC v1] block/NVMe: introduce a new vhost NVMe host device to QEMU

On 15/01/2018 09:01, Changpeng Liu wrote: > NVMe 1.3 specification introduces a new NVMe ADMIN command: > doorbell buffer config, which can write shadow doorbell buffer > instead of MMIO registers, so it can improve the Guest performance > a lot for emulated NVMe devices inside VM. > > Similar

Re: [Qemu-devel] [PATCH x86-next v2] target-i386: add PCID flag to Westmere, Sandy Bridge and Ivy Bridge

[CCing Daniel] On Tue, Jan 16, 2018 at 04:33:00PM +0100, Kashyap Chamarthy wrote: > On Tue, Jan 16, 2018 at 01:55:22PM +0100, Vincent Bernat wrote: > > ❦ 16 janvier 2018 10:41 -0200, Eduardo Habkost  : > > > > >> > Adding Westmere-PCID would require adding a

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/8] s390-ccw: update libc

On 01/16/2018 05:00 AM, Thomas Huth wrote: On 15.01.2018 18:23, Collin L. Walling wrote: On 01/15/2018 12:05 PM, Eric Blake wrote: On 01/15/2018 10:44 AM, Collin L. Walling wrote: [...] +/** + * atoi: + * @str: the string to be converted. + * + * Given a string @str, convert it to an

Re: [Qemu-devel] [PATCH v3 2/8] s390-ccw: ipl structs for eckd cdl/ldl

On 15.01.2018 17:44, Collin L. Walling wrote: > ECKD DASDs have different IPL structures for CDL and LDL > formats. The current Ipl1 and Ipl2 structs follow the CDL > format, so we prepend "EckdCdl" to them. Boot info for LDL > has been moved to a new struct: EckdLdlIpl1. > > Also introduce

[Qemu-devel] [PATCH v2 5/6] qapi: add block-dirty-bitmap-merge

Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 38 ++ include/block/dirty-bitmap.h | 2 ++ block/dirty-bitmap.c | 18 ++ blockdev.c | 30

[Qemu-devel] [PATCH v2 2/6] block/dirty-bitmap: add lock to bdrv_enable/disable_dirty_bitmap

Add locks and remove comments about BQL accordingly to dirty_bitmap_mutex definition in block_int.h. Signed-off-by: Vladimir Sementsov-Ogievskiy --- block/dirty-bitmap.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/block/dirty-bitmap.c

[Qemu-devel] [PATCH v2 3/6] qapi: add block-dirty-bitmap-enable/disable

Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 42 ++ blockdev.c | 42 ++ 2 files changed, 84 insertions(+) diff --git a/qapi/block-core.json

[Qemu-devel] [PATCH v6 0/9] qcow2: cluster space preallocation

(used to be 'qcow2: preallocation and COW improvements') v6: the series is split; now includes only ALLOCATE flag introduction and improvement of qcow2 COW with efficient write-zeroes. File space preallocation beyond EOF will be a separate series. Rebased; remarks to patch 8

[Qemu-devel] [PATCH v6 3/9] block: introduce BDRV_REQ_ALLOCATE flag

The flag is supposed to indicate that the region of the disk image has to be sufficiently allocated so it reads as zeroes. The call with the flag set must return -ENOTSUP if allocation cannot be done efficiently. This has to be made sure of by both - the drivers that support the flag - and

[Qemu-devel] [PATCH v6 2/9] blkverify: set supported write/zero flags

Signed-off-by: Anton Nefedov Reviewed-by: Alberto Garcia --- block/blkverify.c | 9 + 1 file changed, 9 insertions(+) diff --git a/block/blkverify.c b/block/blkverify.c index 06369f9..9ba65d0 100644 --- a/block/blkverify.c +++

[Qemu-devel] [PATCH v6 9/9] iotest 134: test cluster-misaligned encrypted write

COW (even empty/zero) areas require encryption too Signed-off-by: Anton Nefedov --- tests/qemu-iotests/134 | 9 + tests/qemu-iotests/134.out | 10 ++ 2 files changed, 19 insertions(+) diff --git a/tests/qemu-iotests/134 b/tests/qemu-iotests/134

[Qemu-devel] [PATCH v6 4/9] block: treat BDRV_REQ_ALLOCATE as serialising

The idea is that ALLOCATE requests may overlap with other requests. Reuse the existing block layer infrastructure for serialising requests. Use the following approach: - mark ALLOCATE serialising, so subsequent requests to the area wait - ALLOCATE request itself must never wait if another

[Qemu-devel] [PULL 10/24] target/arm: Add fp16 support to vfp_expand_imm

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20180110063337.21538-3-richard.hender...@linaro.org Signed-off-by: Peter Maydell ---

[Qemu-devel] [PULL 09/24] target/arm: Split out vfp_expand_imm

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20180110063337.21538-2-richard.hender...@linaro.org Signed-off-by: Peter Maydell ---

[Qemu-devel] [PULL 20/24] sdhci: rename the SDHC_CAPAB register

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20180115182436.2066-11-f4...@amsat.org Signed-off-by: Peter Maydell --- hw/sd/sdhci-internal.h

[Qemu-devel] [PULL 22/24] sdhci: Implement write method of ACMD12ERRSTS register

From: Andrey Smirnov Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id:

[Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only

From: Philippe Mathieu-Daudé running qtests: $ make check-qtest-arm GTESTER check-qtest-arm SDHC rd_4b @0x44 not implemented SDHC wr_4b @0x40 <- 0x89abcdef not implemented SDHC wr_4b @0x44 <- 0x01234567 not implemented Signed-off-by: Philippe Mathieu-Daudé

[Qemu-devel] [PULL 24/24] sdhci: add a 'dma' property to the sysbus devices

From: Philippe Mathieu-Daudé Add a 'dma' property allowing machine creation to provide the address-space SDHCI DMA operates on. [based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2016.1] Signed-off-by: Philippe Mathieu-Daudé

[Qemu-devel] [PATCH v5 05/14] qapi: Adapt to moved location of 'maketrans' function in py3

Reviewed-by: Eric Blake Signed-off-by: Daniel P. Berrange --- scripts/qapi.py | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/scripts/qapi.py b/scripts/qapi.py index 514cca44bf..1fdd189c0d 100644 --- a/scripts/qapi.py +++

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

On 16/01/2018 13:06, Peter Maydell wrote: >> ASAN is enabled by default if available when --enable-debug. We could >> add more flags if that helps. > Configure switches should work like this: > * default: use feature if present, but don't complain if not present >or not usable > *

[Qemu-devel] [PATCH v5 08/14] qapi: force a UTF-8 locale for running Python

Python2 did not validate locale correctness when reading input data, so would happily read UTF-8 data in non-UTF-8 locales. Python3 is strict so if you try to read UTF-8 data in the C locale, it will raise an error for any UTF-8 bytes that aren't representable in 7-bit ascii encoding. e.g.

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Mon, 2018-01-15 at 17:32 +1100, Suraj Jitindar Singh wrote: > The following patch series adds 3 new tristate capabilities and their > associated handling. > > A new H-Call is implemented which a guest will use to query the > requirement for and availability of workarounds for certain cpu >

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

Hi On Tue, Jan 16, 2018 at 1:06 PM, Peter Maydell wrote: > On 16 January 2018 at 11:58, Marc-André Lureau > wrote: >> Hi >> >> On Tue, Jan 16, 2018 at 12:25 PM, Peter Maydell >> wrote: >>> On 15 January 2018 at

[Qemu-devel] [PATCH v5 06/14] qapi: remove '-q' arg to diff when comparing QAPI output

When the qapi schema tests fail they merely print that the expected output didn't match the actual output. This is largely useless when trying diagnose what went wrong. Removing the '-q' arg to diff means that it is still silent on successful tests, but when it fails we'll see details of the

[Qemu-devel] [PATCH v5 11/14] input: add missing JIS keys to virtio input

From: Miika S keycodemapdb updated to add the QKeyCodes muhenkan and katakanahiragana Signed-off-by: Miika S --- hw/input/virtio-input-hid.c | 7 +++ qapi/ui.json| 5 - ui/keycodemapdb | 2 +- 3 files changed, 12

[Qemu-devel] [PATCH v3 0/4] cryptodev: add vhost support

From: Gonglei I posted the RFC verion a few months ago for DPDK vhost-crypto implmention, and now it's time to send the formal version. Because we need an user space scheme for better performance. The vhost user crypto server side patches had been sent to DPDK

[Qemu-devel] [PATCH v3 1/4] cryptodev: add vhost-user as a new cryptodev backend

From: Gonglei Usage: -chardev socket,id=charcrypto0,path=/path/to/your/socket -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 Signed-off-by: Gonglei Signed-off-by:

[Qemu-devel] [PULL 05/51] i386/cpu/kvm: look at PMU's CPUID before setting MSRs

From: Jan Dakinevich Certain PMU-related MSRs are not supported for CPUs with PMU architecture below version 2. KVM rejects any access to them (see intel_is_valid_msr_idx routine in KVM), and QEMU fails on the following assertion: kvm_put_msrs: Assertion `ret ==

[Qemu-devel] [PULL 20/51] qemu-config: fix leak in query-command-line-options

From: Marc-André Lureau Direct leak of 160 byte(s) in 4 object(s) allocated from: #0 0x55ed7678cda8 in calloc (/home/elmarco/src/qq/build/x86_64-softmmu/qemu-system-x86_64+0x797da8) #1 0x7f3f5e725f75 in g_malloc0

[Qemu-devel] [PULL 13/51] tests/docker: add some sanitizers to fedora dockerfile

From: Marc-André Lureau Build fedora image with ASAN/UBSan support. Signed-off-by: Marc-André Lureau Message-Id: <20180104160523.22995-6-marcandre.lur...@redhat.com> Tested-by: Philippe Mathieu-Daudé Reviewed-by:

[Qemu-devel] [PULL 16/51] vl: fix direct firmware directories leak

From: Marc-André Lureau Note that data_dir[] will now point to allocated strings. Fixes: Direct leak of 16 byte(s) in 1 object(s) allocated from: #0 0x7f1448181850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x7f1446ed8f0c in g_malloc ../glib/gmem.c:94 #2

[Qemu-devel] [PULL 25/51] scsi-disk: release AioContext in unaligned WRITE SAME case

From: Stefan Hajnoczi scsi_write_same_complete() can retry the write if the request was unaligned. Make sure to release the AioContext when that code path is taken! This patch fixes a hang when QEMU terminates after an unaligned WRITE SAME request has been processed with

[Qemu-devel] [PULL 22/51] tests: fix coroutine leak in /basic/entered

From: Marc-André Lureau The coroutine is not finished by the time the test ends, resulting in ASAN warning: ==7005==ERROR: LeakSanitizer: detected memory leaks Direct leak of 312 byte(s) in 1 object(s) allocated from: #0 0x7fd35290fa38 in __interceptor_calloc

[Qemu-devel] [PULL 23/51] mips: fix potential fopen(NULL,...)

From: Marc-André Lureau Spotted thanks to ASAN. Signed-off-by: Marc-André Lureau Message-Id: <20180104160523.22995-18-marcandre.lur...@redhat.com> Signed-off-by: Paolo Bonzini --- hw/nvram/ds1225y.c | 4 ++-- 1

[Qemu-devel] [PULL 18/51] tests: fix migration-test leak

From: Marc-André Lureau Direct leak of 12 byte(s) in 2 object(s) allocated from: #0 0x7f50d403c850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x7f50d1ddf98f in vasprintf (/lib64/libc.so.6+0x8098f) Signed-off-by: Marc-André Lureau

[Qemu-devel] [PULL 24/51] disas/s390: fix global-buffer-overflow

From: Marc-André Lureau Spotted thanks to ASAN: ==25226==ERROR: AddressSanitizer: global-buffer-overflow on address 0x556715a1f120 at pc 0x556714b6f6b1 bp 0x7ffcdfac1360 sp 0x7ffcdfac1350 READ of size 1 at 0x556715a1f120 thread T0 #0 0x556714b6f6b0 in

[Qemu-devel] [PULL 29/51] target/i386: move hflags update code to a function

From: Tao Wu We will share the same code for hax/kvm. Signed-off-by: Tao Wu Message-Id: <20180110195056.85403-1-lep...@google.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 42 ++

[Qemu-devel] [PULL 19/51] crypto: fix stack-buffer-overflow error

From: Marc-André Lureau ASAN complains about: ==8856==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffd8a1fe168 at pc 0x561136cb4451 bp 0x7ffd8a1fe130 sp 0x7ffd8a1fd8e0 READ of size 16 at 0x7ffd8a1fe168 thread T0 #0 0x561136cb4450 in

[Qemu-devel] [PULL 39/51] mips: Tweak location of ';' in macros

From: Eric Blake It is more typical to provide the ';' by the caller of a macro than to embed it in the macro itself; this is because syntax highlight engines can get confused if a macro is called without a semicolon before the closing '}'. Signed-off-by: Eric Blake

[Qemu-devel] [PULL 44/51] checkpatch: Enforce proper do/while (0) style

From: Eric Blake Use of a loop construct for code that is not intended to repeat does not make much idiomatic sense, except in one place: it is a common usage in macros in order to wrap arbitrary code with single-statement semantics. But when used in a macro, it is more

[Qemu-devel] [PULL 32/51] target-i386: update hflags on Hypervisor.framework

This ensures that x86_cpu_dump_state shows registers with the correct size. Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86hvf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index

[Qemu-devel] [PULL 51/51] scripts/analyse-locks-simpletrace.py: script to analyse lock times

From: Alex Bennée This script allows analysis of mutex acquisition and hold times based on a trace file. Given a trace control file of: qemu_mutex_lock qemu_mutex_locked qemu_mutex_unlock And running with: $QEMU $QEMU_ARGS -trace events=./lock-trace You can

[Qemu-devel] [PULL 36/51] cpus: unify qemu_*_wait_io_event

Except for round-robin TCG, every other accelerator is using more or less the same code around qemu_wait_io_event_common. The exception is HAX, which also has to eat the dummy APC that is queued by qemu_cpu_kick_thread. We can add the SleepEx call to qemu_wait_io_event under "if

[Qemu-devel] [PULL 43/51] maint: Fix macros with broken 'do/while(0); ' usage

From: Eric Blake The point of writing a macro embedded in a 'do { ... } while (0)' loop (particularly if the macro has multiple statements or would otherwise end with an 'if' statement) is so that the macro can be used as a drop-in statement with the caller supplying the

[Qemu-devel] [PULL 37/51] irq: fix memory leak

From: linzhecheng entry is moved from list but is not freed. Signed-off-by: linzhecheng Message-Id: <20171225024704.19540-1-linzhech...@huawei.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 1 + 1 file changed,

[Qemu-devel] [PULL 40/51] chardev: Use goto/label instead of do/break/while(0)

From: Eric Blake Use of a do/while(0) control flow in order to permit an early break is an unusual paradigm, and triggers a false positive with a planned future syntax check against 'while (0);'. Rewrite the code to use a goto instead. This patch temporarily keeps an extra

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

Hi On Tue, Jan 16, 2018 at 2:54 PM, Paolo Bonzini wrote: > On 16/01/2018 14:47, Peter Maydell wrote: >> On 16 January 2018 at 13:41, Paolo Bonzini wrote: >>> On 16/01/2018 13:06, Peter Maydell wrote: > ASAN is enabled by default if available when

[Qemu-devel] [PULL 41/51] chardev: Clean up previous patch indentation

From: Eric Blake The previous patch left in an extra scope layer for ease of review; time to remove it. No semantic change. Signed-off-by: Eric Blake Message-Id: <20171201232433.25193-5-ebl...@redhat.com> Reviewed-by: Marc-André Lureau

[Qemu-devel] [PULL 48/51] block/iscsi: fix initialization of iTask in iscsi_co_get_block_status

From: Peter Lieven in case of unaligned requests or on a target that does not support block provisioning we leave iTask uninitialized and check iTask.task for NULL later. Fixes: e38bc23454ef763deb4405ebdee6a1081aa00bc8 Signed-off-by: Peter Lieven Reviewed-by: Eric

[Qemu-devel] [PATCH 2/4] coroutine-lock: convert CoQueue to use QemuLockable

There are cases in which a queued coroutine must be restarted from non-coroutine context (with qemu_co_enter_next). In this cases, qemu_co_enter_next also needs to be thread-safe, but it cannot use a CoMutex and so cannot qemu_co_queue_wait. Use QemuLockable so that the CoQueue can

Re: [Qemu-devel] [PATCH] sun4u: implement power device

Hi Philippe, On 16/01/2018 2:54, Philippe Mathieu-Daudé wrote: CC'ing PCI maintainers. Hi Mark, On 01/15/2018 05:58 PM, Mark Cave-Ayland wrote: This inbuilt device contains a single 4-byte register, of which bit 24 is used to power down the machine on a real Ultra 5. The power device

Re: [Qemu-devel] [PATCH v4 07/14] i.MX: Add i.MX7 GPT variant

On 16 January 2018 at 01:37, Andrey Smirnov wrote: > Add minimal code needed to allow upstream Linux guest to boot. > > Cc: Peter Maydell > Cc: Jason Wang > Cc: Philippe Mathieu-Daudé > Cc:

Re: [Qemu-devel] [PULL 08/51] chardev: introduce qemu_chr_timeout_add_ms()

On Tue, Jan 16, 2018 at 03:16:50PM +0100, Paolo Bonzini wrote: > From: Peter Xu > > It's a replacement of g_timeout_add[_seconds]() for chardevs. Chardevs > now can have dedicated gcontext, we should always bind chardev tasks > onto those gcontext rather than the default main

Re: [Qemu-devel] [PATCH v4 10/14] usb: Add basic code to emulate Chipidea USB IP

On 16 January 2018 at 01:37, Andrey Smirnov wrote: > Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to > work against: > > -usb -drive if=none,id=stick,file=usb.img,format=raw -device \ > usb-storage,bus=usb-bus.0,drive=stick > > Cc: Peter Maydell

[Qemu-devel] [PATCH v2 2/4] default-configs/ppc-softmmu: Restructure the switches according to the machines

Order the CONFIG switches in ppc-softmmu.mak according to the machine classes where they are used (embedded, Mac or PReP), so that it is easier for the users to disable a set of switches completely if they are not needed. Also add the missing CONFIG_IDE_SII3112 switch to the embedded section

Re: [Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

On Tue, Jan 16, 2018 at 06:51:32PM +0800, Wei Wang wrote: > The threshold size is changed to be recorded in s->threshold_size by > commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. > > Signed-off-by: Wei Wang Could you help confirm the commit ID? Since what I see is

[Qemu-devel] [PATCH V6] pci: removed the is_express field since a uniform interface was inserted

according to Eduardo Habkost's commit fd3b02c889 all PCIEs now implement INTERFACE_PCIE_DEVICE so we don't need is_express field anymore. Devices that implements only INTERFACE_PCIE_DEVICE (is_express == 1) or devices that implements only INTERFACE_CONVENTIONAL_PCI_DEVICE (is_express == 0) where

Re: [Qemu-devel] [PATCH v3 3/8] s390-ccw: parse and set boot menu options

On 15.01.2018 17:44, Collin L. Walling wrote: > Set boot menu options for an s390 guest and store them in > the iplb. These options are set via the QEMU command line > option: > > -boot menu=on|off[,splash-time=X] > > or via the libvirt domain xml: > > > > > > Where X

[Qemu-devel] [PATCH v2 6/6] qapi: add disabled parameter to block-dirty-bitmap-add

This is needed, for example, to create a new bitmap and merge several disabled bitmaps into a new one. Without this flag we will have to put block-dirty-bitmap-add and block-dirty-bitmap-disable into one transaction. Signed-off-by: Vladimir Sementsov-Ogievskiy ---

[Qemu-devel] [PATCH v2 4/6] qmp: transaction support for block-dirty-bitmap-enable/disable

Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/transaction.json | 4 +++ blockdev.c| 79 +++ 2 files changed, 83 insertions(+) diff --git a/qapi/transaction.json b/qapi/transaction.json index

[Qemu-devel] [PATCH v2 0/6] qmp dirty bitmap API

Hi all. There are three qmp commands, needed to implement external backup API. Using these three commands, client may do all needed bitmap management by hand: on backup start we need to do a transaction: {disable old bitmap, create new bitmap} on backup success: drop old bitmap on backup

[Qemu-devel] [PATCH v6 6/9] block: support BDRV_REQ_ALLOCATE in passthrough drivers

Support the flag if the underlying BDS supports it Signed-off-by: Anton Nefedov Reviewed-by: Alberto Garcia --- block/blkdebug.c | 3 ++- block/blkverify.c | 2 +- block/mirror.c | 2 +- block/raw-format.c | 3 ++- 4 files changed, 6

[Qemu-devel] [PATCH v6 5/9] file-posix: support BDRV_REQ_ALLOCATE

Current write_zeroes implementation is good enough to satisfy this flag too Signed-off-by: Anton Nefedov Reviewed-by: Alberto Garcia --- block/file-posix.c | 8 1 file changed, 8 insertions(+) diff --git a/block/file-posix.c

[Qemu-devel] [PATCH 04/11] usb-ccid: convert CCIDCardClass::init -> realize

Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/ccid.h | 9 +-- hw/usb/ccid-card-emulated.c | 42 --- hw/usb/ccid-card-passthru.c | 10 hw/usb/dev-smartcard-reader.c | 57 +++

[Qemu-devel] [PATCH 00/11] qdev: remove DeviceClass::init/exit()

Hi, This series finalize the qdev QOMification. We first convert the I2CSlave/SMBusDevice, then the usb-ccid and virtio-ccw, and finally the SysBusDevice. At the end we get one less TODO :) /* TODO remove, once users are converted to unrealize */ There is still one standing in

[Qemu-devel] [PATCH 09/11] qdev: remove DeviceClass::exit

it has no users. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-core.h | 2 -- hw/core/qdev.c | 9 - 2 files changed, 11 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index de063b232f..de7fe2e6e0 100644 ---

Re: [Qemu-devel] [PULL 09/27] migration: calculate vCPU blocktime on dst side

Max Reitz wrote: > On 2018-01-15 12:52, Juan Quintela wrote: >> From: Alexey Perevalov >> >> This patch provides blocktime calculation per vCPU, >> as a summary and as a overlapped value for all vCPUs. >> >> This approach was suggested by Peter Xu,

[Qemu-devel] [PULL 08/24] hw/sd/omap_mmc: Reset SD card on controller reset

Since omap_mmc is still using the legacy SD card API, the SD card created by sd_init() is not plugged into any bus. This means that the controller has to reset it manually. Failing to do this mostly didn't affect the guest since the guest typically does a programmed SD card reset as part of its

[Qemu-devel] [PULL 00/24] target-arm queue

repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116 for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77: sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +

[Qemu-devel] [PULL 16/24] sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20180115182436.2066-7-f4...@amsat.org Signed-off-by: Peter Maydell --- hw/sd/sdhci.c | 22

[Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR

The Configurable Fault Status Register for ARMv7M and v8M is supposed to be byte and halfword accessible, but we were only implementing word accesses. Add support for the other access sizes, which are used by the Zephyr RTOS. Signed-off-by: Peter Maydell Reported-by:

[Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M

For PMSAv7, the v7A/R Arm ARM defines that setting AP to 0b111 is an UNPREDICTABLE reserved combination. However, for v7M this value is documented as having the same behaviour as 0b110: read-only for both privileged and unprivileged. Accept this value on an M profile core rather than treating it

[Qemu-devel] [PULL 23/24] sdhci: fix the PCI device, using the PCI address space for DMA

From: Philippe Mathieu-Daudé While SysBus devices can use the get_system_memory() address space, PCI devices should use the bus master address space for DMA. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé

Re: [Qemu-devel] [PATCHv2 1/2] spapr: Allow some cases where we can't set VSMT mode in the kernel

On Tue, Jan 16, 2018 at 10:20:18AM +0100, Greg Kurz wrote: > On Tue, 16 Jan 2018 15:47:13 +1100 > David Gibson wrote: > > > At present if we require a vsmt mode that's not equal to the kernel's > > default, and the kernel doesn't let us change it (e.g. because it's

[Qemu-devel] [PATCH v5 10/14] configure: allow use of python 3

Signed-off-by: Daniel P. Berrange --- configure | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/configure b/configure index b272a0336b..60b99f45f6 100755 --- a/configure +++ b/configure @@ -1598,9 +1598,8 @@ fi # Note that if the Python

[Qemu-devel] [PATCH v5 09/14] scripts: ensure signrom treats data as bytes

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel P. Berrange --- scripts/signrom.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/signrom.py b/scripts/signrom.py index d1dabe0240..0497a1c32e 100644 ---

[Qemu-devel] [PATCH v3 2/4] cryptodev: add vhost support

From: Gonglei Impliment the vhost-crypto's funtions, such as startup, stop and notification etc. Introduce an enum QCryptoCryptoDevBackendOptionsType in order to identify the cryptodev vhost backend is vhost-user or vhost-kernel-module (If exist). At this point, the

[Qemu-devel] [PULL 12/51] build-sys: compile with -Og or -O1 when --enable-debug

From: Marc-André Lureau When --enable-debug is turned on, configure doesn't set -O level, and uses default compiler -O0 level, which is slow. Instead, use -Og if supported by the compiler (optimize debugging experience), or -O1 (keeps code somewhat debuggable and

[Qemu-devel] [PULL 09/51] build-sys: fix qemu-ga -pthread linking

From: Marc-André Lureau When linking qemu-ga under some configuration (when gthread-2.0.pc doesn't have -pthread, as happening atm with meson build), you may have this linking issue: /usr/bin/ld: libqemuutil.a(qemu-thread-posix.o): undefined reference to symbol

[Qemu-devel] [PULL 17/51] readline: add a free function

From: Marc-André Lureau Fixes leaks such as: Direct leak of 2 byte(s) in 1 object(s) allocated from: #0 0x7eff58beb850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x7eff57942f0c in g_malloc ../glib/gmem.c:94 #2 0x7eff579431cf in g_malloc_n

[Qemu-devel] [PULL 27/51] tests/boot-serial-test: Add a test for the moxiesim machine

From: Thomas Huth Now that moxiesim supports the -bios parameter, we can check this machine in the boot-serial tester, too, by supplying a mini bios that only writes 'T' characters to the UART. Signed-off-by: Thomas Huth Message-Id:

[Qemu-devel] [PULL 21/51] tests: fix qmp-test leak

From: Marc-André Lureau Direct leak of 913 byte(s) in 43 object(s) allocated from: #0 0x55880a15df60 in __interceptor_malloc (/home/elmarco/src/qq/build/tests/qmp-test+0x110f60) #1 0x7f3f20fd098f in _IO_vasprintf (/lib64/libc.so.6+0x8098f) Signed-off-by:

[Qemu-devel] [PULL 31/51] target/i386: hax: Move x86_update_hflags.

From: Tao Wu x86_update_hflags reference env->efer which is updated in hax_get_msrs, so it has to be called after hax_get_msrs. This fix the bug that sometimes dump_state show 32 bits regs even in 64 bits mode. Signed-off-by: Tao Wu Message-Id:

[Qemu-devel] [PULL 35/51] icount: fixed saving/restoring of icount warp timers

From: Pavel Dovgalyuk This patch adds saving and restoring of the icount warp timers in the vmstate. It is needed because there timers affect the virtual clock value. Therefore determinism of the execution in icount record/replay mode depends on determinism of the

[Qemu-devel] [PULL 26/51] tests/boot-serial-test: Add tests for microblaze boards

From: Thomas Huth This adds two simple TCG + UART tests for the microblaze boards, one in big endian mode, and one in little endian mode. Signed-off-by: Thomas Huth Message-Id: <1512031988-32490-5-git-send-email-th...@redhat.com> Signed-off-by: Paolo Bonzini

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