Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/3] Sam460ex emulation

On Sat, 17 Feb 2018, Thomas Huth wrote: On 16.02.2018 11:55, BALATON Zoltan wrote: On Fri, 16 Feb 2018, Thomas Huth wrote: On 15.02.2018 22:27, BALATON Zoltan wrote: Remaining patches for Sam460ex emulation. The original cover letter with more details is here:

[Qemu-devel] [PATCH] intel-iommu: Accept 64-bit writes to FEADDR

From: Jan Kiszka Xen is doing this [1] and currently triggers an abort. [1] http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108 Reported-by: Luis Lloret

Re: [Qemu-devel] [qemu-s390x] [PATCH v7 05/12] s390-ccw: move auxiliary IPL data to separate location

On 16.02.2018 23:07, Collin L. Walling wrote: > The s390-ccw firmware needs some information in support of the > boot process which is not available on the native machine. > Examples are the netboot firmware load address and now the > boot menu parameters. > > While storing that data in unused

Re: [Qemu-devel] [PATCH] kvm: add stubs for kvm_vcpu_id_is_valid() and kvm_arch_vcpu_id()

On 16/02/2018 19:11, Greg Kurz wrote: > These two functions are essentially called by code that is only > compiled when CONFIG_KVM=y, with the notable exception of the > two users in the sPAPR code: > > $ git grep -E -l 'kvm_arch_vcpu_id|kvm_vcpu_id_is_valid' > accel/kvm/kvm-all.c >

Re: [Qemu-devel] [qemu-s390x] [PATCH v7 06/12] s390-ccw: parse and set boot menu options

On 16.02.2018 23:07, Collin L. Walling wrote: > Set boot menu options for an s390 guest and store them in > the iplb. These options are set via the QEMU command line > option: > > -boot menu=on|off[,splash-time=X] > > or via the libvirt domain xml: > > > > > > Where X

Re: [Qemu-devel] [Process] QEMU submaintainers and pull requests

On 16/02/2018 17:09, Cornelia Huck wrote: >> BTW, Fam and I are also planning to improve Patchew so that it is better >> at detecting pull requests and especially merged pull requests. > > Cool. > > Would a certain formatting be helpful for patchew as well? Or do you > plan to parse the cover

Re: [Qemu-devel] [PULL 09/23] gdbstub: Fix vCont behaviour

On 2018-02-17 09:56, Jan Kiszka wrote: > On 2017-02-16 15:31, Paolo Bonzini wrote: >> From: Claudio Imbrenda >> >> When GDB issues a "vCont", QEMU was not handling it correctly when >> multiple VCPUs are active. >> For vCont, for each thread (VCPU), it can be

Re: [Qemu-devel] [PATCH v2] linux-user: make getcpu optional

Le 17/02/2018 à 03:02, Mike Frysinger a écrit : > Not all arches implement this, and the kernel doesn't require them to. > Add ifdef logic to disable it when not available. > > Signed-off-by: Mike Frysinger > --- > linux-user/syscall.c | 4 > 1 file changed, 4

Re: [Qemu-devel] [PULL 09/23] gdbstub: Fix vCont behaviour

On 2017-02-16 15:31, Paolo Bonzini wrote: > From: Claudio Imbrenda > > When GDB issues a "vCont", QEMU was not handling it correctly when > multiple VCPUs are active. > For vCont, for each thread (VCPU), it can be specified whether to > single step, continue or stop

[Qemu-devel] [PATCH] ui: Reorder vte terminal packing to avoid gtk3 warnings

From: Jan Kiszka Fill the terminal box from right to left to avoid Gtk-WARNING **: Allocating size to GtkScrollbar 0x55f6d54b0200 without calling gtk_widget_get_preferred_width/height(). How does the code know the size to allocate? Signed-off-by: Jan Kiszka

Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

I just want to mention that we've been running this patch set in production for a few days, doing hundreds of Fedora RISC-V builds with ‘-smp 4’ and it has been rock solid. Therefore: Tested-by: Richard W.M. Jones Rich. -- Richard Jones, Virtualization Group, Red Hat

[Qemu-devel] [PATCH v2 09/67] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 145 + target/arm/sve_helper.c| 196 - target/arm/translate-sve.c | 65 +++ target/arm/sve.decode |

[Qemu-devel] [PATCH 1/3] hw/i2c-ddc: Do not fail writes

The tx function of the DDC I2C slave emulation was returning 1 on all writes resulting in NACK in the I2C bus. Changing it to 0 makes the DDC I2C work fine with bit-banged I2C such as the versatile I2C. I guess it was not affecting whatever I2C controller this was used with until now, but with

[Qemu-devel] [PATCH 2/3] hw/sii9022: Add support for Silicon Image SII9022

This adds support for emulating the Silicon Image SII9022 DVI/HDMI bridge. It's not very clever right now, it just acknowledges the switch into DDC I2C mode and back. Combining this with the existing DDC I2C emulation gives the right behavior on the Versatile Express emulation passing through the

[Qemu-devel] [PATCH 0/2] tcg: tcg_can_emit_vec_op cleanup+fix

While rearranging/rebasing my SVE patch set, I triggered an assert in tcg_gen_mul_vec. Turns out we should not have gone down that path, due to a missing tcg_can_emit_vec_op check. Tidy the usage of tcg_can_emit_vec_op to avoid code clutter. r~ Richard Henderson (2): tcg: Fold unspecified

Re: [Qemu-devel] [PULL 09/23] gdbstub: Fix vCont behaviour

On 2018-02-17 14:27, Alex Bennée wrote: > > Jan Kiszka writes: > >> On 2018-02-17 09:56, Jan Kiszka wrote: >>> On 2017-02-16 15:31, Paolo Bonzini wrote: From: Claudio Imbrenda When GDB issues a "vCont", QEMU was not handling it

Re: [Qemu-devel] [PATCH 03/11] linux-user/strace: add print_sockaddr_ptr() to handle plain/pointer addrlen

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > since this argument differs between sendto()/recvfrom() > > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.c | 17 +++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git

[Qemu-devel] [PATCH v2 02/67] target/arm: Introduce translate-a64.h

Move some stuff that will be common to both translate-a64.c and translate-sve.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 110 + target/arm/translate-a64.c | 101

[Qemu-devel] [PATCH v2 00/67] target/arm: Scalable Vector Extension

This is 99% of the instruction set. There are a few things missing, notably first-fault and non-fault loads (even these are decoded, but simply treated as normal loads for now). The patch set is dependant on at least 3 other branches. A fully composed tree is available as

[Qemu-devel] [PATCH v2 01/67] target/arm: Enable SVE for aarch64-linux-user

Enable ARM_FEATURE_SVE for the generic "any" cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++ target/arm/cpu64.c | 1 + 2 files changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b3ae62db6..10843994c3 100644

[Qemu-devel] [PATCH v2 18/67] target/arm: Implement SVE Stack Allocation Group

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 24 target/arm/sve.decode | 12 2 files changed, 36 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 13/67] target/arm: Implement SVE bitwise shift by wide elements (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 21 + target/arm/sve_helper.c| 35 +++ target/arm/translate-sve.c | 25 + target/arm/sve.decode | 6 ++ 4

[Qemu-devel] [PATCH v2 10/67] target/arm: Implement SVE Integer Reduction Group

Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 44 + target/arm/sve_helper.c| 95

[Qemu-devel] [PATCH v2 33/67] target/arm: Implement SVE reverse within elements

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve_helper.c| 41 ++--- target/arm/translate-sve.c | 38 ++ target/arm/sve.decode | 7

Re: [Qemu-devel] [PATCH] cuda.h: Fix multiple typedef

On 16/02/18 18:38, Peter Maydell wrote: On 16 February 2018 at 17:31, Dr. David Alan Gilbert (git) wrote: From: "Dr. David Alan Gilbert" RHEL6's compilers don't like the repeated typedef. Signed-off-by: Dr. David Alan Gilbert

Re: [Qemu-devel] [PATCH 06/11] linux-user/strace: improve recvmsg() output

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.list | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/linux-user/strace.list b/linux-user/strace.list > index 947ff04eab..ae6dc8fecf

[Qemu-devel] [PATCH v2 07/67] target/arm: Implement SVE Predicate Logical Operations Group

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 +- target/arm/helper-sve.h| 10 ++ target/arm/sve_helper.c| 39 ++ target/arm/translate-sve.c | 338 - target/arm/sve.decode | 16

[Qemu-devel] [PATCH v2 05/67] target/arm: Implement SVE load vector/predicate

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 132 + target/arm/sve.decode | 22 +++- 2 files changed, 153 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-sve.c

[Qemu-devel] [PATCH v2 36/67] target/arm: Implement SVE Integer Compare - Vectors Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 115 +++ target/arm/sve_helper.c| 193 - target/arm/translate-sve.c | 87 target/arm/sve.decode | 24

[Qemu-devel] [PATCH v2 11/67] target/arm: Implement SVE bitwise shift by immediate (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 25 + target/arm/sve_helper.c| 265 + target/arm/translate-sve.c | 128 ++ target/arm/sve.decode | 29 - 4 files

[Qemu-devel] [PATCH v2 20/67] target/arm: Implement SVE Compute Vector Address Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve_helper.c| 40 target/arm/translate-sve.c | 33 + target/arm/sve.decode | 12 4

[Qemu-devel] [PATCH 1/2] tcg: Fold unspecified opcode test into tcg_can_emit_vec_op

This releases the callers from having to check themselves, which tidies up the code a bit. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 4 tcg/i386/tcg-target.inc.c| 4 tcg/tcg-op-gvec.c| 28

[Qemu-devel] [PATCH v2 16/67] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 41 ++--- target/arm/sve.decode | 13 + 2 files changed, 51 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-sve.c

[Qemu-devel] [PATCH v2 06/67] target/arm: Implement SVE predicate test

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 21 + target/arm/helper.h| 1 + target/arm/sve_helper.c| 77 ++ target/arm/translate-sve.c | 62

[Qemu-devel] [PATCH v2 04/67] target/arm: Implement SVE Bitwise Logical - Unpredicated Group

These were the instructions that were stubbed out when introducing the decode skeleton. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 50 +++--- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git

[Qemu-devel] [PATCH v2 14/67] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 60 + target/arm/sve_helper.c| 127 + target/arm/translate-sve.c | 111 +++

Re: [Qemu-devel] [PATCH v4 00/22] re-factor softfloat and add fp16 functions

Peter Maydell writes: > On 6 February 2018 at 16:47, Alex Bennée wrote: >> Hi, >> >> The main change is applying the __attribute__((flatten)) to some of >> the public functions that show up in Emilio's dbt-benchmark. This >> seems to be a

[Qemu-devel] [PATCH 3/3] arm/vexpress: Add proper display connector emulation

This adds the SiI9022 and EDID I2C devices to the ARM Versatile Express machine, and selects the two I2C devices necessary in the arm-softmmy.mak configuration so everything will build smoothly. I am implementing proper handling of the graphics in the Linux kernel and adding proper emulation of

Re: [Qemu-devel] [PATCH 07/11] linux-user/strace: improve bind() output

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.c| 13 + > linux-user/strace.list | 2 +- > 2 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/linux-user/strace.c

[Qemu-devel] [PATCH v2 15/67] target/arm: Implement SVE Integer Multiply-Add Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 18 ++ target/arm/sve_helper.c| 58 +- target/arm/translate-sve.c | 31 + target/arm/sve.decode | 17

[Qemu-devel] [PATCH v2 03/67] target/arm: Add SVE decode skeleton

Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 +++- target/arm/translate-sve.c | 63 ++ .gitignore

[Qemu-devel] [PATCH 2/2] tcg: Add missing tcg_can_emit_vec_op check in tcg_gen_gvec_2s

This lead to an assertion failure for 64-bit vector multiply, which is not available in the AVX instruction set. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-op-gvec.c

Re: [Qemu-devel] [PATCH 09/11] linux-user/strace: improve capget()/capset() output

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.list | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/linux-user/strace.list b/linux-user/strace.list > index

[Qemu-devel] [PATCH v4 1/1] scripts: Add decodetree.py

To be used to decode ARM SVE, but could be used for any fixed-width ISA. Signed-off-by: Richard Henderson --- Changes since v3: * Add copyright notices. * Do not mark decoder static if --decode is used. Use this option to imply the decoder is the main

[Qemu-devel] [PATCH v2 08/67] target/arm: Implement SVE Predicate Misc Group

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 + target/arm/helper-sve.h| 3 + target/arm/sve_helper.c| 86 +++- target/arm/translate-sve.c | 163 -

[Qemu-devel] [PATCH v2 27/67] target/arm: Implement SVE Permute - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 23 + target/arm/translate-a64.h | 14 +++--- target/arm/sve_helper.c| 114 + target/arm/translate-sve.c | 113

[Qemu-devel] [PATCH v2 12/67] target/arm: Implement SVE bitwise shift by vector (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 27 +++ target/arm/sve_helper.c| 25 + target/arm/translate-sve.c | 4 target/arm/sve.decode | 8 4 files changed, 64

Re: [Qemu-devel] [PULL 09/23] gdbstub: Fix vCont behaviour

Jan Kiszka writes: > On 2018-02-17 09:56, Jan Kiszka wrote: >> On 2017-02-16 15:31, Paolo Bonzini wrote: >>> From: Claudio Imbrenda >>> >>> When GDB issues a "vCont", QEMU was not handling it correctly when >>> multiple VCPUs are active. >>> For

Re: [Qemu-devel] [PATCH 08/11] linux-user/strace: improve gettimeofday() output

Le 24/01/2018 à 14:01, Philippe Mathieu-Daudé a écrit : > Signed-off-by: Philippe Mathieu-Daudé > --- > linux-user/strace.c| 13 + > linux-user/strace.list | 2 +- > 2 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/linux-user/strace.c

[Qemu-devel] [PATCH v2 17/67] target/arm: Implement SVE Index Generation Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 target/arm/sve_helper.c| 40 +++ target/arm/translate-sve.c | 67 ++ target/arm/sve.decode | 14 ++ 4

[Qemu-devel] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extract Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve_helper.c| 81 ++ target/arm/translate-sve.c | 29 + target/arm/sve.decode | 9 +- 4 files changed, 120

[Qemu-devel] [PATCH v2 23/67] target/arm: Implement SVE Element Count Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 11 ++ target/arm/sve_helper.c| 136 ++ target/arm/translate-sve.c | 274 - target/arm/sve.decode | 30 - 4 files

[Qemu-devel] [PATCH v2 22/67] target/arm: Implement SVE floating-point trig select coefficient

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 target/arm/sve_helper.c| 43 +++ target/arm/translate-sve.c | 19 +++ target/arm/sve.decode | 4 4 files changed, 70

[Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 35 +++ target/arm/sve.decode | 8 2 files changed, 43 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 35/67] target/arm: Implement SVE Select Vectors Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 target/arm/sve_helper.c| 55 ++ target/arm/translate-sve.c | 2 ++ target/arm/sve.decode | 6 + 4 files changed, 72

[Qemu-devel] [PATCH v2 38/67] target/arm: Implement SVE Partition Break Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 18 target/arm/sve_helper.c| 247 + target/arm/translate-sve.c | 96 ++ target/arm/sve.decode | 19 4 files changed,

[Qemu-devel] [PATCH v2 60/67] target/arm: Implement SVE FP Fast Reduction Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 35 ++ target/arm/sve_helper.c| 61 ++ target/arm/translate-sve.c | 55 +

[Qemu-devel] [PATCH v9 01/14] hw/arm/smmu-common: smmu base device and datatypes

The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger Signed-off-by: Prem Mallappa ---

[Qemu-devel] [PATCH v9 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk

This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger --- v8 -> v9: - remove guest error log on PTE fetch fault - rename trace functions - fix smmu_page_walk_level_res_invalid_pte last arg - fix PTE_ADDRESS - turn functions into macros - make

[Qemu-devel] [PATCH v2 63/67] target/arm: Implement SVE floating-point trig multiply-add coefficient

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 +++ target/arm/sve_helper.c| 70 ++ target/arm/translate-sve.c | 26 + target/arm/sve.decode | 3 ++ 4 files changed, 103

[Qemu-devel] [PATCH v9 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route

In case the MSI is translated by an IOMMU we need to fixup the MSI route with the translated address. Signed-off-by: Eric Auger --- v5 -> v6: - use IOMMUMemoryRegionClass API It is still unclear to me if we need to register an IOMMUNotifier to handle any change in the

[Qemu-devel] [PATCH 07/19] target/hppa: Convert arithmetic/logical insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 337 ++- target/hppa/insns.decode | 40 ++ 2 files changed, 197 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 14/19] target/hppa: Convert offset memory insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 193 ++- target/hppa/insns.decode | 49 2 files changed, 88 insertions(+), 154 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 12/19] target/hppa: Convert direct and indirect branches

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 125 --- target/hppa/insns.decode | 34 - 2 files changed, 63 insertions(+), 96 deletions(-) diff --git a/target/hppa/translate.c

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/3] ppc: Add aCube Sam460ex board

On Fri, 16 Feb 2018, BALATON Zoltan wrote: On Fri, 16 Feb 2018, David Gibson wrote: On Thu, Feb 15, 2018 at 10:27:06PM +0100, BALATON Zoltan wrote: Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still

[Qemu-devel] [PATCH v2 28/67] target/arm: Implement SVE Permute - Predicates Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 6 + target/arm/sve_helper.c| 280 + target/arm/translate-sve.c | 110 ++ target/arm/sve.decode | 18 +++ 4 files changed, 414

[Qemu-devel] [PATCH v2 19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 12 +++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 81 ++ target/arm/sve.decode | 26 +++ 4 files

[Qemu-devel] [PATCH v2 39/67] target/arm: Implement SVE Predicate Count Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 + target/arm/sve_helper.c| 14 ++ target/arm/translate-sve.c | 116 + target/arm/sve.decode | 27 +++ 4 files changed, 159

[Qemu-devel] [PATCH v2 58/67] target/arm: Implement SVE floating-point arithmetic with immediate

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 56 +++ target/arm/sve_helper.c| 68 ++ target/arm/translate-sve.c | 73 ++

[Qemu-devel] [PATCH v2 52/67] target/arm: Implement SVE store vector/predicate register

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 101 + target/arm/sve.decode | 6 +++ 2 files changed, 107 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 30/67] target/arm: Implement SVE compress active elements

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 +++ target/arm/sve_helper.c| 34 ++ target/arm/translate-sve.c | 12 target/arm/sve.decode | 6 ++ 4 files changed, 55 insertions(+)

[Qemu-devel] [PATCH v2 49/67] target/arm: Implement SVE FP Multiply-Add Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 ++ target/arm/sve_helper.c| 53 ++ target/arm/translate-sve.c | 41 +++ target/arm/sve.decode | 17

[Qemu-devel] [PATCH 1/2] hw/net: Add support for Intel pch_gbe ethernet

This patch introduces support for emulating the ethernet controller found in the Intel EG20T Platform Controller Hub, referred to as pch_gbe for consistency with both Linux & U-Boot. Documentation for the hardware can be found here:

[Qemu-devel] [PATCH v2 56/67] target/arm: Implement SVE scatter store vector immediate

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 79 +++--- target/arm/sve.decode | 11 +++ 2 files changed, 65 insertions(+), 25 deletions(-) diff --git a/target/arm/translate-sve.c

[Qemu-devel] [PATCH v9 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers

We introduce some helpers to handle wired IRQs and especially GERROR interrupt. SMMU writes GERROR register on GERROR event and SW acks GERROR interrupts by setting GERRORn. The Wired interrupts are edge sensitive hence the pulse usage. Signed-off-by: Eric Auger --- v7

[Qemu-devel] [PATCH 0/2] MIPS Boston / pch_gbe ethernet support

This short series introduces support for emulating the ethernet controller found in the Intel EG20T Platform Controller Hub, and then enables that device for the MIPS Boston board. This gives the Boston board a network device matching that found on real Boston boards, providing unmodified Boston

[Qemu-devel] [PATCH 18/19] target/hppa: Convert fp operate insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 757 --- target/hppa/insns.decode | 175 +++ 2 files changed, 498 insertions(+), 434 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 19/19] target/hppa: Merge translate_one into hppa_tr_translate_insn

Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH v2 21/67] target/arm: Implement SVE floating-point exponential accelerator

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 +++ target/arm/sve_helper.c| 81 ++ target/arm/translate-sve.c | 22 + target/arm/sve.decode | 7 4 files changed, 114

[Qemu-devel] [PATCH v2 43/67] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 +++ target/arm/helper.h| 19 ++ target/arm/translate-sve.c | 41 target/arm/vec_helper.c| 94 ++

[Qemu-devel] [PATCH v2 25/67] target/arm: Implement SVE Integer Wide Immediate - Predicated Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve_helper.c| 108 + target/arm/translate-sve.c | 92 ++ target/arm/sve.decode | 17

[Qemu-devel] [PATCH v2 54/67] target/arm: Implement SVE prefetches

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 9 + target/arm/sve.decode | 23 +++ 2 files changed, 32 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index

[Qemu-devel] [PATCH v2 62/67] target/arm: Implement SVE FP Compare with Zero Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 42 ++ target/arm/sve_helper.c| 45 + target/arm/translate-sve.c | 41 +

Re: [Qemu-devel] [PATCH 3/3] arm/vexpress: Add proper display connector emulation

Hi Linus, On 02/17/2018 11:00 AM, Linus Walleij wrote: > This adds the SiI9022 and EDID I2C devices to the ARM Versatile > Express machine, and selects the two I2C devices necessary in the > arm-softmmy.mak configuration so everything will build smoothly. > > I am implementing proper handling of

[Qemu-devel] [PATCH v2 51/67] target/arm: Implement SVE load and broadcast element

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve_helper.c| 43 target/arm/translate-sve.c | 55 +- target/arm/sve.decode | 5 + 4

[Qemu-devel] [PATCH v2 50/67] target/arm: Implement SVE Floating Point Accumulating Reduction Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 7 ++ target/arm/sve_helper.c| 56 ++ target/arm/translate-sve.c | 42 ++ target/arm/sve.decode | 5 + 4

[Qemu-devel] [PATCH v9 14/14] hw/arm/virt: Handle iommu in 2.12 machine type

The new machine type exposes a new "iommu" virt machine option. The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3. Signed-off-by: Eric Auger --- v7 -> v8: - Revert to machine option, now dubbed "iommu", preparing for virtio instantiation. v5 -> v6:

[Qemu-devel] [PATCH v9 06/14] hw/arm/smmuv3: Queue helpers

We introduce helpers to read/write into the command and event circular queues. smmuv3_write_eventq and smmuv3_cmq_consume will become static in subsequent patches. Invalidation commands are not yet dealt with. We do not cache data that need to be invalidated. This will change with vhost

[Qemu-devel] [PATCH v9 07/14] hw/arm/smmuv3: Implement MMIO write operations

Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger --- v7 -> v8: - precise in the commit message invalidation commands are not yet treated. - use new queue helpers - do not decode unhandled

[Qemu-devel] [PATCH 06/19] target/hppa: Convert memory management insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 159 +++ target/hppa/insns.decode | 38 +++ 2 files changed, 88 insertions(+), 109 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 05/19] target/hppa: Unify specializations of OR

With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 108 +++- 1 file changed, 60

[Qemu-devel] [PATCH 11/19] target/hppa: Convert shift, extract, deposit insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 217 ++- target/hppa/insns.decode | 15 2 files changed, 96 insertions(+), 136 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH 17/19] target/hppa: Convert fp fused multiply-add insns

Signed-off-by: Richard Henderson --- target/hppa/translate.c | 79 target/hppa/insns.decode | 12 2 files changed, 38 insertions(+), 53 deletions(-) diff --git a/target/hppa/translate.c

[Qemu-devel] [PATCH v3] ppc: Add aCube Sam460ex board

Add emulation of aCube Sam460ex board based on AMCC 460EX embedded SoC. This is not a complete implementation yet with a lot of components still missing but enough for the U-Boot firmware to start and to boot a Linux kernel or AROS. Signed-off-by: François Revol Signed-off-by:

[Qemu-devel] [PATCH] target/m68k: TCGv returned by gen_load() must be freed

Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 70c7583621..cb795ed25b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@

[Qemu-devel] [PATCH v2 47/67] target/arm: Implement SVE integer convert to floating-point

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 30 +++ target/arm/sve_helper.c| 52 ++ target/arm/translate-sve.c | 92 ++ target/arm/sve.decode | 22

[Qemu-devel] [PATCH v2 29/67] target/arm: Implement SVE Permute - Interleaving Group

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 15 ++ target/arm/sve_helper.c| 72 ++ target/arm/translate-sve.c | 69 target/arm/sve.decode

[Qemu-devel] [PATCH v2 34/67] target/arm: Implement SVE vector splice (predicated)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 2 ++ target/arm/sve_helper.c| 37 + target/arm/translate-sve.c | 10 ++ target/arm/sve.decode | 3 +++ 4 files changed, 52 insertions(+) diff

[Qemu-devel] [PATCH v2 67/67] target/arm: Implement SVE floating-point unary operations

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve_helper.c| 8 target/arm/translate-sve.c | 28 target/arm/sve.decode | 4 4 files changed, 54 insertions(+) diff

[Qemu-devel] [PATCH v2 61/67] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group

Signed-off-by: Richard Henderson --- target/arm/helper.h| 8 target/arm/translate-sve.c | 43 +++ target/arm/vec_helper.c| 20 target/arm/sve.decode | 5 + 4 files changed,

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