On 04/04/2018 05:30 PM, Eric Auger wrote:
> The 567b5b309abe ("vfio/pci: Relax DMA map errors for MMIO regions")
> added an error message if a passed memory section address or size
> is not aligned to the page size and thus cannot be DMA mapped.
>
> This patch fixes the trace by printing the
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
fma-single: 74.73 MFlops
fma-double: 74.54 MFlops
- after:
fma-single: 203.37 MFlops
fma-double: 169.37 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
fma-single: 23.24 MFlops
fma-double: 23.70 MFlops
- after:
This will allow us to run correctness tests against our
FP implementation. The test can be run in two modes (called
"testers"): host and soft. With the former we check the results
and FP flags on the host machine against the model.
With the latter we check QEMU's fpu primitives against the
model.
Before 8936006 ("fpu/softfloat: re-factor minmax", 2018-02-21),
we used to return +Zero for maxnummag(-Zero,+Zero); after that
commit, we return -Zero.
Fix it by making {min,max}nummag consistent with {min,max}num,
deferring to the latter when the absolute value of the operands
is the same.
With
On Wed, Apr 04, 2018 at 19:11:13 -0400, Emilio G. Cota wrote:
(snip)
> +if (likely((soft_t ## _is_normal(a) || soft_t ## _is_zero(a)) && \
> + (soft_t ## _is_normal(b) || soft_t ## _is_zero(b)) && \
> + (soft_t ## _is_normal(c) || soft_t ## _is_zero(c))
On 04/05/2018 10:07 AM, Richard Henderson wrote:
> On 04/05/2018 02:49 AM, Emilio G. Cota wrote:
>> 1. grab this binary:
>> http://cs.columbia.edu/~cota/qemu/nbench-aarch64
>> 2. run it on a PowerPC host with:
>> $ aarch64-linux-user/qemu-aarch64 nbench-aarch64 -V
>>
>> Note: the "-V" (or
The only place we test this flag is in conjunction with
ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
Signed-off-by: David Gibson
Reviewed-by: Cédric Le Goater
The #if isn't necessary, because there's a suitable one inside
ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
functions that search and register them. So by the time we get to realize
having an invalid one indicates a code error, not a user error, so an
assert() is
Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.
We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.
Signed-off-by:
The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
flag into the PPCHash64Options structure.
Signed-off-by: David Gibson
There are a couple places (one generic, one target specific) where we need
to get the host page size associated with a particular memory backend. I
have some upcoming code which will add another place which wants this. So,
for convenience, add a helper function to calculate this.
preadv/pwritev accept low and high parts of file offset in two separate
parameters. When host bitness doesn't match guest bitness these parts
must be appropriately recombined.
Introduce target_low_high_to_host_low_high that does this recombination
and use it in preadv/pwritev syscalls.
This fixes
On 4 April 2018 at 23:41, Stefan Hajnoczi wrote:
> On Tue, Apr 03, 2018 at 11:30:33AM +0800, Fam Zheng wrote:
> > On Tue, 04/03 13:17, Lindsay Mathieson wrote:
> > > On 3 April 2018 at 13:11, Fam Zheng wrote:
> > >
> > > > On Tue, 04/03 12:59, Lindsay
These macros were introduced to deal with the fact that the mmu_model
field has bit flags mixed in with what's otherwise an enum of various mmu
types.
We've now eliminated all those flags except for one, and that one -
POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
we
On Thu, 5 Apr 2018 10:53:38 +1000
Alexey Kardashevskiy wrote:
> On 5/4/18 9:09 am, Alex Williamson wrote:
> > On Wed, 4 Apr 2018 22:30:50 +0200
> > Eric Auger wrote:
> >
> >> The 567b5b309abe ("vfio/pci: Relax DMA map errors for MMIO regions")
> >>
Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well. This makes which bits of the
field should be compared pretty confusing.
Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR -
This series makes some small changes to make it easier to obtain the
host page size backing given portions of guest RAM. We use this in a
couple of places currently, and I have one or two more to add in some
upcoming code.
Changes since v1:
* Reworked design based on Eduardo's feedback
*
On Wed, Apr 04, 2018 at 07:35:17PM -0700, no-re...@patchew.org wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20180405022002.17809-1-da...@gibson.dropbear.id.au
> Subject: [Qemu-devel] [PATCHv2
On 04/05/2018 11:33 AM, Max Filippov wrote:
> +static void target_low_high_to_host_low_high(abi_ulong tlow,
> + abi_ulong thigh,
> + unsigned long *hlow,
> + unsigned
On 04/05/2018 11:41 AM, Max Filippov wrote:
> +static void target_low_high_to_host_low_high(abi_ulong tlow,
> + abi_ulong thigh,
> + unsigned long *hlow,
> + unsigned
glibc >= 2.25 defines canonicalize in commit eaf5ad0
(Add canonicalize, canonicalizef, canonicalizel., 2016-10-26).
Given that we'll be including soon, prepare
for this by prefixing our canonicalize() with sf_ to avoid
clashing with the libc's canonicalize().
Reported-by: Bastian Koppelmann
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
sqrt-single: 43.27 MFlops
sqrt-double: 24.81 MFlops
- after:
sqrt-single: 297.94 MFlops
sqrt-double: 210.46 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
sqrt-single: 12.41 MFlops
sqrt-double: 6.22 MFlops
-
Cc: Bastian Koppelmann
Signed-off-by: Emilio G. Cota
---
target/tricore/fpu_helper.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index df16290..31df462
The appended paves the way for leveraging the host FPU for a subset
of guest FP operations. For most guest workloads (e.g. FP flags
aren't ever cleared, inexact occurs often and rounding is set to the
default [to nearest]) this will yield sizable performance speedups.
The approach followed here
On Thu, Mar 01, 2018 at 17:53:44 -0500, Emilio G. Cota wrote:
> [ What is this all about? See this message:
> http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
(snip)
> You can fetch this series from:
> https://github.com/cota/qemu/tree/trloop-conv-v1
*ping* on this series.
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1522883475-27858-1-git-send-email-c...@braap.org
Subject: [Qemu-devel] [PATCH v3 00/15] fp-test + hardfloat
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git
ASAN reported:
hw/block/pflash_cfi02.c:245:33: runtime error: index 82 out of bounds for
type 'uint8_t [82]'
Since the 'cfi_len' member is not used, remove it to keep the code safer.
Reported-by: AddressSanitizer
Signed-off-by: Philippe Mathieu-Daudé
---
On 5/4/18 9:09 am, Alex Williamson wrote:
> On Wed, 4 Apr 2018 22:30:50 +0200
> Eric Auger wrote:
>
>> The 567b5b309abe ("vfio/pci: Relax DMA map errors for MMIO regions")
>> added an error message if a passed memory section address or size
>> is not aligned to the page
Here's a set of cleanups for the ppc cpu code. Most are related
specifically to the 64-bit hash MMU, but there are some others as
well.
In particular it establishes a new structure PPCHash64Options which
contains details of the hash64 mmu which can vary from one cpu to
another. This attempts to
Currently some cpus set the hash64_opts field in the class structure, with
specific details of their variant of the 64-bit hash mmu. For the
remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
But there are only a couple of cpus that use those fallbacks, so just have
them to
As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
change will make some things simpler later on.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
Reviewed-by: Cédric Le Goater
---
hw/ppc/fdt.c | 5
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180405022002.17809-1-da...@gibson.dropbear.id.au
Subject: [Qemu-devel] [PATCHv2
Hi Thomas,
On 04/04/2018 04:15 PM, Thomas Huth wrote:
> An instance_init function must not fail - and might be called multiple times,
> e.g. during device introspection with the 'device-list-properties' QMP
> command. Since the integratorcm device ignores this rule, QEMU currently
> aborts in
This will allow us to measure the performance impact of FP emulation
optimizations. Note that we can measure both directly the impact
on the softfloat functions (with "-t soft"), or the impact on an
emulated workload (call with "-t host" and run under qemu user-mode).
Signed-off-by: Emilio G.
On Wed, Apr 04, 2018 at 19:11:14 -0400, Emilio G. Cota wrote:
(snip)
> +if (likely((soft_t ## _is_normal(a) || soft_t ## _is_zero(a)) && \
Updated on the github tree to:
-if (likely((soft_t ## _is_normal(a) || soft_t ## _is_zero(a)) && \
+if (likely(soft_t ##
CPU definitions for cpus with the 64-bit hash MMU can include a table of
available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
However, it turns out all the cpus which support 64K pages already include
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180405022002.17809-1-da...@gibson.dropbear.id.au
Subject: [Qemu-devel] [PATCHv2 for-2.13 0/2] Helpers to obtain host page sizes
for guest RAM
=== TEST SCRIPT BEGIN ===
Signed-off-by: Philippe Mathieu-Daudé
---
Sadly I'm missing something, this does not work.
memory.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/memory.c b/memory.c
index eaa5fa7f23..ae45ea7779 100644
--- a/memory.c
+++ b/memory.c
@@
Priorities can be negative, fix this limitation.
Signed-off-by: Philippe Mathieu-Daudé
---
memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/memory.c b/memory.c
index e77f9e4036..eaa5fa7f23 100644
--- a/memory.c
+++ b/memory.c
@@ -1258,7 +1258,7 @@
v2: https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg06805.html
Changes since v2:
- Add R-b tags
- Add a patch to rename our canonicalize to sf_canonicalize,
to avoid clashing with glibc's.
- Add a patch to define float{32,64}_is_zero_or_normal
- Simplify the
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 2.12 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-2.12.0-rc2.tar.xz
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
div-single: 34.84 MFlops
div-double: 34.04 MFlops
- after:
div-single: 275.23 MFlops
div-double: 216.38 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
div-single: 9.33 MFlops
div-double: 9.30 MFlops
- after:
These will gain some users very soon.
Signed-off-by: Emilio G. Cota
---
include/fpu/softfloat.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index a8512fb..66985e1 100644
--- a/include/fpu/softfloat.h
+++
On 04/05/2018 02:49 AM, Emilio G. Cota wrote:
> 1. grab this binary:
> http://cs.columbia.edu/~cota/qemu/nbench-aarch64
> 2. run it on a PowerPC host with:
> $ aarch64-linux-user/qemu-aarch64 nbench-aarch64 -V
>
> Note: the "-V" (or "-v") flag is important! Without it, there's no segfault.
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180405012241.25714-1-f4...@amsat.org
Subject: [Qemu-devel] [RFC PATCH v2 0/4] memory:
At the moment the device tree produced by the H_CAS handler has no
reserved map initialized at all which is not correct as at least one
empty record is required to be present as a marker of the end.
This does not cause problems now as the only consumer is SLOF which
does not look at the reserved
On Wed, 4 Apr 2018 22:30:50 +0200
Eric Auger wrote:
> The 567b5b309abe ("vfio/pci: Relax DMA map errors for MMIO regions")
> added an error message if a passed memory section address or size
> is not aligned to the page size and thus cannot be DMA mapped.
>
> This patch
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
mul-single: 126.91 MFlops
mul-double: 118.28 MFlops
- after:
mul-single: 258.02 MFlops
mul-double: 197.96 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
mul-single: 37.42 MFlops
mul-double: 38.77 MFlops
-
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
cmp-single: 113.01 MFlops
cmp-double: 115.54 MFlops
- after:
cmp-single: 527.83 MFlops
cmp-double: 457.21 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
cmp-single: 39.32 MFlops
cmp-double: 39.80 MFlops
-
If an user creates a RAM region smaller than TARGET_PAGE_SIZE,
this region will be handled as a subpage.
While the subpage behavior can be noticed by an experienced QEMU
developper, it might takes hours to a novice to figure it out.
To save time to novices, do not allow subpage creation via the
ASan reported:
shift exponent 4294967280 is too large for 64-bit type 'long unsigned int'
...
runtime error: shift exponent -16 is negative
This can occurs when MemoryRegionOps .valid.min_access_size <
.impl.min_access_size,
for example if a guest uses a 16-bit operand to access a
Hi, these are few memory related patches.
Patch #2 v1 was:
http://lists.gnu.org/archive/html/qemu-devel/2017-08/msg02255.html
I'll send the related qtests in v3.
Patch #4 is a failed attempt to change a region priority at runtime.
Phil.
Philippe Mathieu-Daudé (4):
memory: Avoid to create
preadv/pwritev accept low and high parts of file offset in two separate
parameters. When host bitness doesn't match guest bitness these parts
must be appropriately recombined.
Introduce target_low_high_to_host_low_high that does this recombination
and use it in preadv/pwritev syscalls.
This fixes
The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer).
This is another static-after-initialization parameter of the specific
version of the 64-bit hash MMU in the CPU. So, this patch folds the field
into PPCHash64Options with the other hash MMU options.
This is a bit more
This paves the way for upcoming work.
Cc: Bastian Koppelmann
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/fpu/softfloat.h | 20
1 file changed, 20 insertions(+)
diff --git
These are a few muladd-related operations that the original IBM syntax
does not specify; model files for these are in muladd.fptest.
Signed-off-by: Emilio G. Cota
---
tests/fp/fp-test.c | 24
tests/fp/muladd.fptest | 51
Performance results (single and double precision) for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
add-single: 135.07 MFlops
add-double: 131.60 MFlops
sub-single: 130.04 MFlops
sub-double: 133.01 MFlops
- after:
add-single: 443.04 MFlops
add-double: 301.95 MFlops
sub-single:
env->sps contains page size encoding information as an embedded structure.
Since this information is specific to 64-bit hash MMUs, split it out into
a separately allocated structure, to reduce the basic env size for other
cpus. Along the way we make a few other cleanups:
* Rename to
In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
CPUPPCState.
For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
In theory this makes more work for the functions, but since "cs",
qemu_mempath_getpagesize() gets the effective (host side) page size for
a block of memory backed by an mmap()ed file on the host. It requires
the mem_path parameter to be non-NULL.
This ends up meaning all the callers need a different case for handling
anonymous memory (for memory-backend-ram or
Because of the various hooks called some variant on "init" - and the rather
greater number that used to exist, I'm always wondering when a function
called simply "*_init" or "*_initfn" will be called.
To make it easier on myself, and maybe others, rename the instance_init
hooks for ppc cpus to
On Thu, Apr 05, 2018 at 12:07:38PM +1000, Alexey Kardashevskiy wrote:
> At the moment the device tree produced by the H_CAS handler has no
> reserved map initialized at all which is not correct as at least one
> empty record is required to be present as a marker of the end.
> This does not cause
On 5/4/18 11:22 am, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Sadly I'm missing something, this does not work.
What does not work precisely? memory_region_set_priority() is not called or
visit_type_int32() does not return priority, etc?
>
>
An instance_init function must not fail - and might be called multiple times,
e.g. during device introspection with the 'device-list-properties' QMP
command. Since the integratorcm device ignores this rule, QEMU currently
aborts in this case (though it really should not):
echo
Am 04.04.2018 um 10:48 hat Vladimir Sementsov-Ogievskiy geschrieben:
> 03.04.2018 16:54, Kevin Wolf wrote:
> > Am 30.03.2018 um 17:16 hat Vladimir Sementsov-Ogievskiy geschrieben:
> > > Add an assert (we don't want set both arguments) and remove
> > > duplication.
> > >
> > > Signed-off-by:
On Wed, Mar 28, 2018 at 08:32:35PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> When debugging a coredump, pthread_self can't be obtained from
> function arch_prctl. Moreover if qemu crashed in coroutine, we
> can't find 'start_thread' in current stack-trace. So, add a method,
> actually proposed
Am 30.03.2018 um 17:16 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Blacklist these formats, as they don't support image creation, as they
> say:
> > ./qemu-img create -f bochs x 1m
> qemu-img: x: Format driver 'bochs' does not support image creation
>
> > ./qemu-img create -f
Max Filippov writes:
> Hi Alex,
>
> On Tue, Apr 3, 2018 at 9:26 AM, Alex Bennée wrote:
>> Max Filippov writes:
>>
>>> cpu_copy adds newly created CPU object to container/machine/unattached,
>>> but does it w/o proper locking. As
Aleksandar Markovic writes:
> From: Aleksandar Markovic
>
> Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64.
>
> Signed-off-by: Miodrag Dinic
> Signed-off-by: Aleksandar Markovic
Hi
Please, send any topic that you are interested in covering.
At the end of Monday I will send an email with the agenda or the
cancellation of the call, so hurry up.
After discussions on the QEMU Summit, we are going to have always open a
KVM call where you can add topics.
Call details:
Paolo Bonzini writes:
> Except for round-robin TCG, every other accelerator is using more or
> less the same code around qemu_wait_io_event_common. The exception
> is HAX, which also has to eat the dummy APC that is queued by
> qemu_cpu_kick_thread.
>
> We can add the
Use the 'select-frame' GDB command to switch stacks instead of manually
setting the debugged thread's registers (this only works when debugging
a live process, not in a coredump).
Cc: Vladimir Sementsov-Ogievskiy
Signed-off-by: Stefan Hajnoczi
---
Not sharing code from precopy/unix because we have to read back the
tcp parameter.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
---
tests/migration-test.c | 83
On 3 April 2018 at 15:01, Eduardo Habkost wrote:
> The following changes since commit f184de7553272223d6af731d7d623a7cebf710b5:
>
> Merge remote-tracking branch
> 'remotes/riscv/tags/riscv-qemu-2.12-critical-fixes' into staging (2018-03-31
> 09:42:33 +0100)
>
> are
It will be used to store the uri parameters. We want this only for
tcp, so we don't set it for other uris. We need it to know what port
is migration running.
Signed-off-by: Juan Quintela
--
This used to be uri parameter, but it has so many troubles to
reproduce that it
1) What's this
When the migration capability 'bypass-shared-memory'
is set, the shared memory will be bypassed when migration.
It is the key feature to enable several excellent features for
the qemu, such as qemu-local-migration, qemu-live-update,
extremely-fast-save-restore, vm-template,
Ping for code review, please? It would be nice if our 'raspi3'
model for 2.12 was one we could say actually booted a known
Linux image...
thanks
-- PMM
On 19 March 2018 at 16:15, Peter Maydell wrote:
> This patchset fixes the code in the bcm2835_sdhost device
> so that
Aleksandar Markovic writes:
> From: Goran Ferenc
>
> Hold BQL whenever mips_vpe_wake() is invoked.
>
> Without this patch, MIPS MT with MTTCG enabled triggers an abort in
> tcg_handle_interrupt() due to an unlocked access to
Aleksandar Markovic writes:
> From: Miodrag Dinic
>
> While testing mttcg VP0 could get stuck in a loop waiting for other
> VPs to come up (which never actually happens). To fix this, kick VPs
> while they are being powered up by Cluster
Aleksandar Markovic writes:
> From: Aleksandar Markovic
>
> v1->v2:
>
> - patches #3 and #4 are squashed into one to avoid bisect breaking
> - improved locking features in patch #5 (formerly #6)
> - commit messages reviewed and
On 04/04/2018 12:34, Alex Bennée wrote:
>
> Paolo Bonzini writes:
>
>> Except for round-robin TCG, every other accelerator is using more or
>> less the same code around qemu_wait_io_event_common. The exception
>> is HAX, which also has to eat the dummy APC that is queued
On Wed, Apr 04, 2018 at 11:27:09AM +0200, BALATON Zoltan wrote:
> On Mon, 2 Apr 2018, BALATON Zoltan wrote:
> > Now that we have a mirror of this repo on git.qemu.org change the
> > submodule to use that and also update it to latest HEAD which has a
> > commit to fix a dangling symlink.
> >
> >
On 02/04/2018 18:36, Tony Krowiak wrote:
On 03/26/2018 05:03 AM, Pierre Morel wrote:
On 26/03/2018 10:32, David Hildenbrand wrote:
On 16.03.2018 00:24, Tony Krowiak wrote:
If the CPU model indicates that AP facility is installed on
the guest (i.e., -cpu ,ap=on), then the expectation is
On 02/04/2018 16:13, Programmingkid wrote:
>
>> On Apr 2, 2018, at 10:07 AM, qemu-devel-requ...@nongnu.org wrote:
>>
>> Message: 2
>> Date: Mon, 2 Apr 2018 04:22:52 +0200
>> From: Paolo Bonzini
>> To: Rainer M?ller , qemu-devel@nongnu.org
>> Subject: Re:
On 04/04/2018 12:23, Alex Bennée wrote:
>
>> From: Aleksandar Markovic
>>
>> Make sure BQL is held for all interrupt requests.
>>
>> For MTTCG-enabled configurations, handling soft and hard interrupts
>> between vCPUs must be properly locked. By acquiring BQL, make
On Wed, Mar 28, 2018 at 09:34:35PM +0800, linzhecheng wrote:
> Check device having the feature of VIRTIO_CONSOLE_F_EMERG_WRITE before
> get config->emerg_wr. It is neccessary because sizeof(virtio_console_config)
> is 8 byte if VirtIOSerial doesn't have the feature of
>
On 28/03/2018 19:32, Vladimir Sementsov-Ogievskiy wrote:
> When debugging a coredump, pthread_self can't be obtained from
> function arch_prctl. Moreover if qemu crashed in coroutine, we
> can't find 'start_thread' in current stack-trace. So, add a method,
> actually proposed in 1138f24645e9e,
Am 03.04.2018 um 23:03 hat Jeff Cody geschrieben:
> On Tue, Apr 03, 2018 at 06:33:52PM +0200, Kevin Wolf wrote:
> > The legacy command line interface gets the socket path from an option
> > called 'socket'. QAPI in contract uses SocketAddress, where the
> > corresponding option is called 'path'.
>
On Wed, Mar 28, 2018 at 08:32:36PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> - print regs
> - catch exception for coredump debugging
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> scripts/qemugdb/coroutine.py | 18 ++
> 1 file changed, 14
On 4 April 2018 at 11:27, Alex Bennée wrote:
> I'm wondering if it should be doing more. After all start/end_exclusive
> rely on the cpu list and that isn't updated on thread creation - and
> without that a bunch of other things fail like ld/st exclusive after
> your first
Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
---
tests/migration-test.c | 64 ++
1 file changed, 64 insertions(+)
diff --git a/tests/migration-test.c b/tests/migration-test.c
index
No need to write it to a file. Just need a proper firmware O:-)
Signed-off-by: Juan Quintela
CC: Laurent Vivier
---
tests/migration-test.c | 41 +
1 file changed, 5 insertions(+), 36 deletions(-)
diff --git
Hi Peter,
On 03/19/2018 01:15 PM, Peter Maydell wrote:
> Add some tracepoints to the bcm2835_sdhost driver, to assist
> debugging.
>
> Signed-off-by: Peter Maydell
> ---
> hw/sd/bcm2835_sdhost.c | 10 ++
> hw/sd/trace-events | 6 ++
> 2 files changed,
Am 03.04.2018 um 22:52 hat Dr. David Alan Gilbert geschrieben:
> * Kevin Wolf (kw...@redhat.com) wrote:
> > Am 28.03.2018 um 19:02 hat Dr. David Alan Gilbert (git) geschrieben:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > Activating the block devices causes the locks to
On 3 April 2018 at 11:35, Laurent Vivier wrote:
> The following changes since commit f184de7553272223d6af731d7d623a7cebf710b5:
>
> Merge remote-tracking branch
> 'remotes/riscv/tags/riscv-qemu-2.12-critical-fixes' into staging (2018-03-31
> 09:42:33 +0100)
>
> are available
Aleksandar Markovic writes:
> From: Aleksandar Markovic
>
> Make sure BQL is held for all interrupt requests.
>
> For MTTCG-enabled configurations, handling soft and hard interrupts
> between vCPUs must be properly locked. By
Abdallah Bouassida writes:
> This is a preparation for the coming feature of creating dynamically an XML
> description for the ARM sysregs.
> A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML.
> This bit is enabled automatically when
On 03/04/2018 11:36, Cornelia Huck wrote:
On Mon, 2 Apr 2018 12:36:27 -0400
Tony Krowiak wrote:
On 03/26/2018 05:03 AM, Pierre Morel wrote:
On 26/03/2018 10:32, David Hildenbrand wrote:
On 16.03.2018 00:24, Tony Krowiak wrote:
+/*
+ * The Query
Migration code needs that function in hmp.c (so we need to export it),
and it needs it on tests/migration-test.c, so we need to move it to a
place where it is compiled into the test framework.
Signed-off-by: Juan Quintela
---
chardev/char-socket.c | 29
Hi
New in v8:
- SocketAddress is now a list (a.k.a make happy danp)
- Rebase on top of upstream
network listener is *interesting*
- *HACK* to make SocketAddress list in common
see patch: create-socket-paramenter
Please review, Juan.
CC: berra...@redhat.com
[v7]
This is v6, it differest
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