[Qemu-devel] [PATCH v2 06/10] intel-iommu: pass in address space when page walk

We pass in the VTDAddressSpace to replace the aw bits when doing page walk. The VTDAddressSpace contains the aw bits information, meanwhile we'll need to do something more in the follow up patches regarding to the address spaces. Signed-off-by: Peter Xu ---

Re: [Qemu-devel] [PATCH v2 00/10] intel-iommu: nested vIOMMU, cleanups, bug fixes

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180504030811.28111-1-pet...@redhat.com Subject: [Qemu-devel] [PATCH v2 00/10] intel-iommu: nested vIOMMU, cleanups, bug fixes === TEST SCRIPT BEGIN === #!/bin/bash

Re: [Qemu-devel] [PATCH v3 07/35] spapr/xive: introduce the XIVE Event Queues

On Thu, May 03, 2018 at 04:37:29PM +0200, Cédric Le Goater wrote: > On 05/03/2018 08:25 AM, David Gibson wrote: > > On Thu, May 03, 2018 at 08:07:54AM +0200, Cédric Le Goater wrote: > >> On 05/03/2018 07:45 AM, David Gibson wrote: > >>> On Thu, Apr 26, 2018 at 11:48:06AM +0200, Cédric Le Goater

Re: [Qemu-devel] [PATCH 42/67] tcg: use include "tcg.h" consistently

On 05/03/2018 10:51 PM, Michael S. Tsirkin wrote: Some places include tcg.h, others tcg/tcg.h. Let's be consistent. Signed-off-by: Michael S. Tsirkin --- include/exec/translator.h | 2 +- trace/mem.h | 2 +- accel/stubs/tcg-stub.c| 2 +-

[Qemu-devel] [PATCH 01/13] target-openrisc: Write back result before FPE exception

From: Richard Henderson The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Reviewed-by: Bastian Koppelmann

[Qemu-devel] [PATCH 04/13] target/openrisc: Convert memory insns

Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 275 +-- target/openrisc/insns.decode | 24 2 files changed, 160 insertions(+), 139 deletions(-) diff --git a/target/openrisc/translate.c

[Qemu-devel] [PATCH 00/13] target/openrisc: Convert to decodetree.py

While the openrisc decode isn't particularly complicated, the result, I think, is still cleaner. r~ Richard Henderson (13): target-openrisc: Write back result before FPE exception target/openrisc: Start conversion to decodetree.py target/openrisc: Convert branch insns target/openrisc:

Re: [Qemu-devel] [PATCH 08/10] intel-iommu: maintain per-device iova ranges

On Fri, Apr 27, 2018 at 11:37:24PM +, Tian, Kevin wrote: [...] > > Self NAK on this... > > > > More than half of the whole series tries to solve the solo problem > > that we unmapped some pages that were already mapped, which proved > > to > > be wrong. Now if we squash the change we will

Re: [Qemu-devel] [PATCH v3 07/35] spapr/xive: introduce the XIVE Event Queues

On 05/03/2018 07:45 AM, David Gibson wrote: > On Thu, Apr 26, 2018 at 11:48:06AM +0200, Cédric Le Goater wrote: >> On 04/26/2018 09:25 AM, David Gibson wrote: >>> On Thu, Apr 19, 2018 at 02:43:03PM +0200, Cédric Le Goater wrote: The Event Queue Descriptor (EQD) table is an internal table of

Re: [Qemu-devel] [PATCH v2 0/5] checkpatch: backport UTF-8 fixes and MAINTAINERS check

On Tue, 05/01 14:04, Stefan Hajnoczi wrote: > On Mon, Apr 30, 2018 at 05:56:30AM -0700, no-re...@patchew.org wrote: > > === OUTPUT BEGIN === > > Checking PATCH 1/5: checkpatch: add a --strict check for utf-8 in commit > > logs... > > WARNING: line over 80 characters > > #101: FILE:

[Qemu-devel] [PATCH 8/8] spapr: Clean up handling of LPCR power-saving exit bits

To prevent spurious wakeups on cpus that are supposed to be disabled, we need to clear the LPCR bits which control certain wakeup events. spapr_cpu_reset() has separate cases here for boot and non-boot (initially inactive) cpus. rtas_start_cpu() then turns the LPCR bits on when the non-boot cpus

[Qemu-devel] [PATCH 6/8] target/ppc: Delay initialization of LPCR_UPRT for secondary cpus

In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are initialized based on on ppc64_radix_guest(). Which seems reasonable, except that ppc64_radix_guest() is based on spapr->patb_entry which is only set up in spapr_machine_reset, called _after_ cpu_ppc_set_papr() for boot

[Qemu-devel] [PATCH 7/8] spapr: Move PAPR mode cpu setup fully to spapr code

cpu_ppc_set_papr() does several things: 1) it sets up the virtual hypervisor interface 2) it prevents the cpu from ever entering hypervisor mode 3) it tells KVM that we're emulating a cpu in PAPR mode and 4) it configures the LPCR and AMOR (hypervisor privileged registers) so

[Qemu-devel] [PATCH 0/8] spapr: Cleanups to startup and LPCR handling

This is an assortment of patches cleaning up how we handle startup / entry of CPUs for the pseries machine type. In particular it makes a number of cleanups to the way we manage the LPCR register. I've posted versions of most of these patches before, however there have been enough reworks and

[Qemu-devel] [PATCH 5/8] spapr: Clean up LPCR updates from hypercalls

There are several places in spapr_hcall.c where we need to update the LPCR value on all CPUs. We do this with the set_spr() helper. That's not really correct because this directly sets the SPR value, without going through the ppc_store_lpcr() helper which may need to update state based on the

[Qemu-devel] [PATCH 4/8] spapr: Make a helper to set up cpu entry point state

Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify

Re: [Qemu-devel] [PATCH qemu] qom: Document qom/device-list-properties implementation specific

On 2/5/18 7:50 pm, Paolo Bonzini wrote: > On 02/05/2018 11:33, Alexey Kardashevskiy wrote: >>> +# Note: the handler creates an object, enumerates properties and >>> destroys >>> +# the object so it only lists properties created in >>> TypeInfo::instance_init(). >>> +# Since

[Qemu-devel] [PATCH 1/8] target/ppc: Add ppc_store_lpcr() helper

There are some fields in the cpu state which need to be updated when the LPCR register is changed, which is done by ppc_hash64_update_rmls() and ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to call them afterwards to make sure the state is up to date. That's easy to get

Re: [Qemu-devel] [PATCH for-2.13 02/10] spapr: Remove support for PowerPC 970 with pseries machine type

On Fri, Apr 20, 2018 at 02:25:23PM +0200, Greg Kurz wrote: > On Tue, 17 Apr 2018 17:17:14 +1000 > David Gibson wrote: > > > Current POWER cpus allow for a VRMA, a special mapping which describes a > > guest's view of memory when in real mode (MMU off, from the

Re: [Qemu-devel] [PATCH v2 1/2] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA

On Wed, May 02, 2018 at 10:06:39PM +0200, Francisco Iglesias wrote: > Add a model of the generic DMA found on Xilinx ZynqMP. Hi Francisco, A few more comments: > > Signed-off-by: Francisco Iglesias > Signed-off-by: Edgar E. Iglesias >

[Qemu-devel] [PATCH 2/8] spapr: Clean up rtas_start_cpu() & rtas_stop_self()

This makes several minor cleanups to these functions: * Follow usual convention of an early exit on error, rather than having most of the body in an if * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the RTAS call is invoked, newcpu is the cpu which we're starting

Re: [Qemu-devel] [PATCH v3 07/35] spapr/xive: introduce the XIVE Event Queues

On Thu, May 03, 2018 at 08:07:54AM +0200, Cédric Le Goater wrote: > On 05/03/2018 07:45 AM, David Gibson wrote: > > On Thu, Apr 26, 2018 at 11:48:06AM +0200, Cédric Le Goater wrote: > >> On 04/26/2018 09:25 AM, David Gibson wrote: > >>> On Thu, Apr 19, 2018 at 02:43:03PM +0200, Cédric Le Goater

[Qemu-devel] [PATCH 3/8] spapr: Remove unhelpful helpers from rtas_start_cpu()

rtas_start_cpu() calls spapr_cpu_update_tb_offset() and spapr_cpu_set_endianness() to initialize certain things in the new cpu's state. This is the only caller of those helpers, and they're each only a few lines long, so we might as well just fold them into the caller. In addition, those helpers

[Qemu-devel] [PATCH] usb-host: skip open on pending postload bh

usb-host emulates a device unplug after live migration, because the device state is unknown and unplug/replug makes sure the guest re-initializes the device into a working state. This can't be done in post-load though, so post-load just schedules a bottom half which executes after vmload is

Re: [Qemu-devel] [PATCH 2/3] block/file-posix: File locking during creation

On Sat, 04/28 13:03, Max Reitz wrote: > On 2018-04-27 08:22, Fam Zheng wrote: > > On Sat, 04/21 00:09, Max Reitz wrote: > >> When creating a file, we should take the WRITE and RESIZE permissions. > >> We do not need either for the creation itself, but we do need them for > >> clearing and resizing

Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines

On Thu, May 03, 2018 at 07:52:32AM +0200, Cédric Le Goater wrote: > On 05/03/2018 02:58 AM, David Gibson wrote: > > On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote: > >> On 04/24/2018 02:03 PM, Cédric Le Goater wrote: > +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu) > +{ >

Re: [Qemu-devel] [PATCH 1/4] qemu-options: Remove remainders of the -tdf option

Thomas Huth writes: > The -tdf options has been removed with d07aa197c5a1556449361a0cbb5108e2, > but apparently I forgot to remove the corresponding two lines from > qemu-options.hx. > > Signed-off-by: Thomas Huth > --- > qemu-options.hx | 3 --- > 1 file

Re: [Qemu-devel] [PATCH 2/4] qemu-options: Remove deprecated -no-kvm-pit-reinjection

Thomas Huth writes: > Deprecated since the beginning when it was added for compatibility with > the ancient qemu-kvm fork of QEMU, and it even printed out the deprecation > warning since right from the start (i.e. QEMU v1.3.0), so it's really time > to remove this now. > >

[Qemu-devel] [PATCH] spapr: Remove support for explicitly allocated RMAs

Current POWER cpus allow for a VRMA, a special mapping which describes a guest's view of memory when in real mode (MMU off, from the guest's point of view). Older cpus didn't have that which meant that to support a guest a special host-contiguous region of memory was needed to give the guest its

Re: [Qemu-devel] [PATCH 2/8] spapr: Clean up rtas_start_cpu() & rtas_stop_self()

On 05/03/2018 08:21 AM, David Gibson wrote: > This makes several minor cleanups to these functions: > * Follow usual convention of an early exit on error, rather than having > most of the body in an if > * Clearer naming of cpu and cpu_. Now callcpu is the cpu from which the > RTAS

Re: [Qemu-devel] [PATCH] spapr: Remove support for explicitly allocated RMAs

On 03.05.2018 09:10, David Gibson wrote: > Current POWER cpus allow for a VRMA, a special mapping which describes a > guest's view of memory when in real mode (MMU off, from the guest's point > of view). Older cpus didn't have that which meant that to support a guest > a special host-contiguous

Re: [Qemu-devel] [PATCH 08/10] intel-iommu: maintain per-device iova ranges

On 2018年05月03日 14:04, Peter Xu wrote: IMHO the guest can't really detect this, but it'll found that the device is not working functionally if it's doing something like what Jason has mentioned. Actually now I have had an idea if we really want to live well even with Jason's example: maybe

Re: [Qemu-devel] [PATCH 07/10] util: implement simple interval tree logic

On 2018年05月03日 15:10, Peter Xu wrote: On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote: [...] +int it_tree_remove(ITTree *tree, ITValue start, ITValue end) +{ +ITRange range = { .start = start, .end = end }, *overlap, and; +GTree *gtree; + +g_assert(tree); + +gtree

Re: [Qemu-devel] [PATCH 5/8] spapr: Clean up LPCR updates from hypercalls

On 05/03/2018 08:21 AM, David Gibson wrote: > There are several places in spapr_hcall.c where we need to update the LPCR > value on all CPUs. We do this with the set_spr() helper. That's not > really correct because this directly sets the SPR value, without going > through the ppc_store_lpcr()

Re: [Qemu-devel] [PATCH 08/10] intel-iommu: maintain per-device iova ranges

On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote: > > > On 2018年05月03日 14:04, Peter Xu wrote: > > IMHO the guest can't really detect this, but it'll found that the > > device is not working functionally if it's doing something like what > > Jason has mentioned. > > > > Actually now I

Re: [Qemu-devel] [PATCH 7/8] spapr: Move PAPR mode cpu setup fully to spapr code

On 05/03/2018 08:21 AM, David Gibson wrote: > cpu_ppc_set_papr() does several things: > 1) it sets up the virtual hypervisor interface > 2) it prevents the cpu from ever entering hypervisor mode > 3) it tells KVM that we're emulating a cpu in PAPR mode > and 4) it configures the LPCR

Re: [Qemu-devel] [PATCH 07/10] util: implement simple interval tree logic

On Thu, May 03, 2018 at 03:21:13PM +0800, Jason Wang wrote: > > > On 2018年05月03日 15:10, Peter Xu wrote: > > On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote: > > > > [...] > > > > > > +int it_tree_remove(ITTree *tree, ITValue start, ITValue end) > > > > +{ > > > > +ITRange range

Re: [Qemu-devel] [PATCH v2 0/2] block/file-posix: allow -drive cache.direct=off live migration

On Fri, 04/27 17:23, Stefan Hajnoczi wrote: > v2: > * Add comment on !__linux__ situation [Fam] > * Add file-posix.c x-check-cache-dropped=on|off option [DaveG, Kevin] Reviewed-by: Fam Zheng

Re: [Qemu-devel] [PATCH 08/10] intel-iommu: maintain per-device iova ranges

On 2018年05月03日 15:28, Peter Xu wrote: On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote: On 2018年05月03日 14:04, Peter Xu wrote: IMHO the guest can't really detect this, but it'll found that the device is not working functionally if it's doing something like what Jason has mentioned.

Re: [Qemu-devel] [PATCH 8/8] spapr: Clean up handling of LPCR power-saving exit bits

On 05/03/2018 08:21 AM, David Gibson wrote: > To prevent spurious wakeups on cpus that are supposed to be disabled, we > need to clear the LPCR bits which control certain wakeup events. > spapr_cpu_reset() has separate cases here for boot and non-boot (initially > inactive) cpus. rtas_start_cpu()

Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines

On 05/03/2018 08:36 AM, David Gibson wrote: > On Thu, May 03, 2018 at 07:52:32AM +0200, Cédric Le Goater wrote: >> On 05/03/2018 02:58 AM, David Gibson wrote: >>> On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote: On 04/24/2018 02:03 PM, Cédric Le Goater wrote: >> +hwaddr

Re: [Qemu-devel] [PATCH v2] migration: introduce decompress-error-check

On Thu, May 03, 2018 at 04:06:11PM +0800, guangrong.x...@gmail.com wrote: > From: Xiao Guangrong > > QEMU 2.13 enables strict check for compression & decompression to > make the migration more robust, that depends on the source to fix > the internal design which

Re: [Qemu-devel] [PATCH 1/4] nbd: Prepare for additional block sizing info

02.05.2018 00:13, Eric Blake wrote: The NBD spec is clarifying [1] that a server may want to advertise different limits for READ/WRITE (in our case, 32M) than for TRIM/ZERO (in our case, nearly 4G). Add the constants and name lookups for new NBD_INFO_ fields used during handshake to convey this

Re: [Qemu-devel] [PATCH 1/8] target/ppc: Add ppc_store_lpcr() helper

On 05/03/2018 08:21 AM, David Gibson wrote: > There are some fields in the cpu state which need to be updated when the > LPCR register is changed, which is done by ppc_hash64_update_rmls() and > ppc_hash64_update_vrma(). Code which alters env->spr[SPR_LPCR] needs to > call them afterwards to make

Re: [Qemu-devel] [PATCH 4/4] qemu-options: Remove deprecated -no-kvm

Thomas Huth writes: > We've never documented this option in our qemu-doc, so unless the users > used qemu-kvm before, they never should never have been aware of this You're serious about "never", aren't you? ;-> > option. It's been marked as deprecated in the source code

Re: [Qemu-devel] [PATCH 3/4] qemu-options: Remove deprecated -no-kvm-irqchip

Thomas Huth writes: > We've never documented this option in our qemu-doc, so unless the users > used qemu-kvm before, they never should never have been aware of this > option. It's been marked as deprecated in the source code since a long > time already, and officially marked

Re: [Qemu-devel] [PATCH 07/10] util: implement simple interval tree logic

On Fri, Apr 27, 2018 at 01:53:35PM +0800, Jason Wang wrote: [...] > > +int it_tree_remove(ITTree *tree, ITValue start, ITValue end) > > +{ > > +ITRange range = { .start = start, .end = end }, *overlap, and; > > +GTree *gtree; > > + > > +g_assert(tree); > > + > > +gtree =

Re: [Qemu-devel] [PATCH 3/8] spapr: Remove unhelpful helpers from rtas_start_cpu()

On 05/03/2018 08:21 AM, David Gibson wrote: > rtas_start_cpu() calls spapr_cpu_update_tb_offset() and > spapr_cpu_set_endianness() to initialize certain things in the new cpu's > state. This is the only caller of those helpers, and they're each only > a few lines long, so we might as well just

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Wed, May 02, 2018 at 09:02:00AM +0100, Daniel P. Berrangé wrote: > On Wed, May 02, 2018 at 09:44:03AM +0200, Gerd Hoffmann wrote: > > Hi, > > > > > > If we bump the major version each year anyway, why not go the whole way > > > > and use 2018.1, 2018.2, ... (or even .)? The nice thing > > >

Re: [Qemu-devel] [PATCH 6/8] target/ppc: Delay initialization of LPCR_UPRT for secondary cpus

On 05/03/2018 08:21 AM, David Gibson wrote: > In cpu_ppc_set_papr() the UPRT and GTSE bits of the LPCR default value are > initialized based on on ppc64_radix_guest(). Which seems reasonable, > except that ppc64_radix_guest() is based on spapr->patb_entry which is > only set up in

Re: [Qemu-devel] [PATCH 1/8] target/ppc: Add ppc_store_lpcr() helper

On Thu, May 03, 2018 at 09:06:42AM +0200, Cédric Le Goater wrote: > On 05/03/2018 08:21 AM, David Gibson wrote: > > There are some fields in the cpu state which need to be updated when the > > LPCR register is changed, which is done by ppc_hash64_update_rmls() and > > ppc_hash64_update_vrma().

Re: [Qemu-devel] [PATCH 08/10] intel-iommu: maintain per-device iova ranges

On Thu, May 03, 2018 at 03:43:35PM +0800, Jason Wang wrote: > > > On 2018年05月03日 15:28, Peter Xu wrote: > > On Thu, May 03, 2018 at 03:20:11PM +0800, Jason Wang wrote: > > > > > > On 2018年05月03日 14:04, Peter Xu wrote: > > > > IMHO the guest can't really detect this, but it'll found that the > >

[Qemu-devel] [PATCH v2] migration: introduce decompress-error-check

From: Xiao Guangrong QEMU 2.13 enables strict check for compression & decompression to make the migration more robust, that depends on the source to fix the internal design which triggers the unexpected error conditions To make it work for migrating old version QEMU

Re: [Qemu-devel] [PATCH v2] migration: introduce decompress-error-check

On 05/03/2018 04:06 PM, guangrong.x...@gmail.com wrote: From: Xiao Guangrong QEMU 2.13 enables strict check for compression & decompression to make the migration more robust, that depends on the source to fix the internal design which triggers the unexpected error

Re: [Qemu-devel] [RFC 0/7] block: Try to use correctly typed blockdev options

Max Reitz writes: > (Sorry, Markus, sorry, Kevin, if this series makes you angry.) Anger? Nah. Gallows humor :) > The subject says it all, I think. The original issue I was assigned to > solve is this: > > $ ./qemu-img info --image-opts driver=null-co,size=42 >

Re: [Qemu-devel] [PATCH 2/4] nbd/client: Refactor in preparation for more limits

02.05.2018 00:13, Eric Blake wrote: The next patch will ask the server for more items of NBD_INFO. However, the server is free to respond with INFO items in a different order than what we request, so performing any sanity checks about constraints that occur between multiple INFO items must be

Re: [Qemu-devel] [PATCH v2 02/19] spapr: introduce a skeleton for the XIVE interrupt controller

On 05/03/2018 04:29 AM, David Gibson wrote: > On Thu, Apr 26, 2018 at 10:17:13AM +0200, Cédric Le Goater wrote: >> On 04/26/2018 07:36 AM, David Gibson wrote: >>> On Thu, Apr 19, 2018 at 07:40:09PM +0200, Cédric Le Goater wrote: On 04/16/2018 06:26 AM, David Gibson wrote: > On Thu, Apr

[Qemu-devel] [PATCH 0/2] arm: Add nRF51 SoC and micro:bit machine

Hello, This short series implements a minimal definition of the Nordic Semiconductor nRF51, a Cortex-M0 ARM SoC, and the BBC micro:bit, a machine that will use this SoC. This work will serve as the base for our Google Summer of Code and Outreachy interns who will work on implementing a number of

[Qemu-devel] [PATCH 1/2] arm: Add Nordic Semiconductor nRF51 SoC

The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley

[Qemu-devel] [PATCH 2/2] arm: Add BBC micro:bit machine

This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Signed-off-by: Joel Stanley --- hw/arm/Makefile.objs | 2 +-

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote: > On Wed, May 02, 2018 at 09:02:00AM +0100, Daniel P. Berrangé wrote: > > On Wed, May 02, 2018 at 09:44:03AM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > > If we bump the major version each year anyway, why not go the whole

Re: [Qemu-devel] [PATCH v5 1/2] slirp: Add "query-usernet" QMP command

On Thu, May 03, 2018 at 09:25:45AM +0800, Fam Zheng wrote: > HMP "info usernet" has been available but it isn't ideal for programmed > use cases. This closes the gap in QMP by adding a counterpart > "query-usernet" command. It is basically translated from > the HMP slirp_connection_info() loop,

Re: [Qemu-devel] [PATCH 3/4] nbd/client: Support requests of additional block sizing info

02.05.2018 00:13, Eric Blake wrote: The NBD spec is clarifying [1] that a server may want to advertise different limits for READ/WRITE (in our case, 32M) than for TRIM/ZERO (in our case, nearly 4G). Implement the client side support for these alternate limits, by always requesting the new

Re: [Qemu-devel] [PATCH 0/2] arm: Add nRF51 SoC and micro:bit machine

Hi, This series failed docker-build@min-glib build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180503090532.3113-1-j...@jms.id.au Subject: [Qemu-devel] [PATCH 0/2] arm: Add nRF51

[Qemu-devel] [PATCH v1 00/29] target-microblaze: Add support for Extended Addressing

From: "Edgar E. Iglesias" This series adds support for Extended Addressing to our MicroBlaze models. It adds both the non-MMU load/store EA and the extended MMU addressing. There are several ways to implement this but since there are further 64-bit extensions in the

Re: [Qemu-devel] [PATCH 1/2] arm: Add Nordic Semiconductor nRF51 SoC

On 3 May 2018 at 10:05, Joel Stanley wrote: > The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, > plus other common ARM SoC peripherals. > > http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf > > This defines a basic model of the CPU and memory, with no

[Qemu-devel] [PATCH v1 03/29] target-microblaze: compute_ldst_addr: Use bool instead of int

From: "Edgar E. Iglesias" Use bool instead of int to represent flags. No functional change. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Qemu-devel] [PATCH v1 01/29] target-microblaze: dec_load: Use bool instead of unsigned int

From: "Edgar E. Iglesias" Use bool instead of unsigned int to represent flags. No functional change. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff

[Qemu-devel] [PATCH v1 09/29] target-microblaze: Conditionalize setting of PVR11_USE_MMU

From: "Edgar E. Iglesias" Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Signed-off-by: Edgar E. Iglesias ---

[Qemu-devel] [PATCH v1 02/29] target-microblaze: dec_store: Use bool instead of unsigned int

From: "Edgar E. Iglesias" Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 7

[Qemu-devel] [PATCH v1 05/29] target-microblaze: Correct special register array sizes

From: "Edgar E. Iglesias" Correct special register array sizes. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 4 ++-- target/microblaze/translate.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff

[Qemu-devel] [PATCH v1 10/29] target-microblaze: Bypass MMU with MMU_NOMMU_IDX

From: "Edgar E. Iglesias" Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Signed-off-by: Edgar E. Iglesias --- target/microblaze/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v1 07/29] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage

From: "Edgar E. Iglesias" Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Signed-off-by: Edgar E. Iglesias ---

[Qemu-devel] [PATCH v1 04/29] target-microblaze: Fallback to our latest CPU version

From: "Edgar E. Iglesias" Today, when running QEMU in linux-user or with boards that don't select a specific CPU version, we treat it as an invalid version and log a message. Instead, if no specific version was selected, fallback to our latest CPU version.

[Qemu-devel] [PATCH v1 23/29] target-microblaze: Implement MFSE EAR

From: "Edgar E. Iglesias" Implement MFSE EAR to enable access to the upper part of EAR. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v1 13/29] target-microblaze: Use TCGv for load/store addresses

From: "Edgar E. Iglesias" Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 2 +-

Re: [Qemu-devel] [Qemu-block] [PATCH 3/3] block: Removed unused sector-based blocking I/O

On Fri 27 Apr 2018 05:43:33 PM CEST, Eric Blake wrote: >>> -static int bdrv_rw_co(BdrvChild *child, int64_t sector_num, uint8_t *buf, >>> - int nb_sectors, bool is_write, BdrvRequestFlags >>> flags) >>> -{ >>> -QEMUIOVector qiov; >>> -struct iovec iov = { >>> -

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Thu, May 03, 2018 at 10:26:40AM +0100, Peter Maydell wrote: > On 3 May 2018 at 10:07, Daniel P. Berrangé wrote: > > On Thu, May 03, 2018 at 08:21:00AM +0100, Stefan Hajnoczi wrote: > >> I don't see an issue with time-based numbering schemes. Ubuntu made it > >> popular

Re: [Qemu-devel] [PATCH v3 06/35] spapr/xive: introduce a XIVE interrupt presenter model

On 05/03/2018 07:39 AM, David Gibson wrote: > On Thu, Apr 26, 2018 at 07:15:29PM +0200, Cédric Le Goater wrote: >> On 04/26/2018 11:27 AM, Cédric Le Goater wrote: >>> On 04/26/2018 09:11 AM, David Gibson wrote: On Thu, Apr 19, 2018 at 02:43:02PM +0200, Cédric Le Goater wrote: > [snip] >

[Qemu-devel] [PATCH V2 2/3] riscv: htif: increase the priority of the htif subregion

The htif device is supposed to be mapped over an other subregion. So increase its priority to one to avoid any conflict. Here is the output of info mtree: Before: (qemu) info mtree address-space: memory - (prio 0, i/o): system

[Qemu-devel] [PATCH V2 0/3] riscv: some little fix.

Hi all, Here are some fixes for RISCV. The two firsts allow to map the HTIF @0x. The third one requires fdt to be present on the build machine so the build doesn't end with a linker error. Thanks, Fred KONRAD Frederic (3): riscv: spike: allow base == 0 riscv: htif: increase the

[Qemu-devel] [PATCH V2 1/3] riscv: spike: allow base == 0

The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark Signed-off-by: KONRAD Frederic --- V1 -> V2: * Check that both symbols are set as suggested

Re: [Qemu-devel] [Qemu-arm] [PATCH 4/9] tcg: Introduce atomic helpers for integer min/max

On 05/03/2018 10:26 AM, Peter Maydell wrote: >> It won't be compiled for the 32-bit host. Translation will not attempt to >> use >> this helper and will instead call exit_atomic. > > OK. Can you point me at the code that handles min/max atomics in that case? exit_atomic raises EXP_ATOMIC,

Re: [Qemu-devel] [PATCH v1 02/29] target-microblaze: dec_store: Use bool instead of unsigned int

On 05/03/2018 02:18 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Use bool instead of unsigned int to represent flags. > Also, use extract32 instead of open coding the bit extract. > > No functional change. > > Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH v1 01/29] target-microblaze: dec_load: Use bool instead of unsigned int

On 05/03/2018 02:18 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Use bool instead of unsigned int to represent flags. > No functional change. > > Signed-off-by: Edgar E. Iglesias > --- > target/microblaze/translate.c | 7

Re: [Qemu-devel] [PATCH v1 03/29] target-microblaze: compute_ldst_addr: Use bool instead of int

On 05/03/2018 02:18 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Use bool instead of int to represent flags. > No functional change. > > Signed-off-by: Edgar E. Iglesias > --- > target/microblaze/translate.c | 10 +-

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Thu, May 03, 2018 at 04:16:41PM +0200, Cédric Le Goater wrote: > Coming back to the initial motivation that Peter pointed out, would > the goal to be able to run vcpus of different architectures ? It would > certainly be interesting to model a platform, specially if we can > synchronize the

[Qemu-devel] [PULL 0/8] RDMA queue

The following changes since commit 59255887e6cafeff747250d2613003a41d1d9dff: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180502' into staging (2018-05-03 11:25:14 +0100) are available in the Git repository at: https://github.com/marcel-apf/qemu tags/rdma-pull-request for you

[Qemu-devel] [PULL 5/8] hw/rdma: Fix possible out of bounds access to regs array

From: Yuval Shaia Coverity (CID1390589, CID1390608). Array size is RDMA_BAR1_REGS_SIZE, let's make sure the given address is in range. While there also: 1. Adjust the size of this bar to reasonable size 2. Report the size of the array with sizeof(array) Reported-by:

[Qemu-devel] [PULL 1/8] hw/rdma: Fix possible munmap call on a NULL pointer

Coverity CID 1390620: we call munmap() on a NULL pointer. Reported-by: Peter Maydell Signed-off-by: Marcel Apfelbaum Reviewed-by: Yuval Shaia Message-Id: <20180430200223.4119-2-marcel.apfelb...@gmail.com> ---

Re: [Qemu-devel] [PATCH v1 13/29] target-microblaze: Use TCGv for load/store addresses

On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Use TCGv for load/store addresses, allowing for future > computation of 64-bit load/store address. > > No functional change. > > Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH v1 17/29] target-microblaze: dec_msr: Use bool and extract32

On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Use bool and extract32 to represent the to, clr and > clrset flags. > > No functional change. > > Signed-off-by: Edgar E. Iglesias > --- >

Re: [Qemu-devel] [PATCH v1 16/29] target-microblaze: Break out trap_illegal()

On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Break out trap_illegal() to handle illegal operation traps. > We now generally stop translation of the current insn if > it's not valid. > > Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Thu, May 03, 2018 at 04:06:19PM +0200, Thomas Huth wrote: > On 03.05.2018 15:43, Gerd Hoffmann wrote: > > On Thu, May 03, 2018 at 10:26:40AM +0100, Peter Maydell wrote: > >> On 3 May 2018 at 10:07, Daniel P. Berrangé wrote: > >>> On Thu, May 03, 2018 at 08:21:00AM +0100,

Re: [Qemu-devel] release retrospective, next release timing, numbering

On 05/03/2018 11:45 AM, Daniel P. Berrangé wrote: > On Thu, May 03, 2018 at 11:42:23AM +0200, Thomas Huth wrote: >> On 03.05.2018 11:33, Daniel P. Berrangé wrote: >>> On Wed, May 02, 2018 at 01:05:21PM +0100, Peter Maydell wrote: On 2 May 2018 at 12:58, Daniel P. Berrangé

Re: [Qemu-devel] release retrospective, next release timing, numbering

On Thu, 3 May 2018 16:06:19 +0200 Thomas Huth wrote: > On 03.05.2018 15:43, Gerd Hoffmann wrote: > > On Thu, May 03, 2018 at 10:26:40AM +0100, Peter Maydell wrote: > >> On 3 May 2018 at 10:07, Daniel P. Berrangé wrote: > >>> On Thu, May 03, 2018 at

Re: [Qemu-devel] [Qemu-arm] [PATCH 9/9] target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only

On 27 April 2018 at 01:26, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index

Re: [Qemu-devel] [PATCH v1 1/2] target-arm: Add the Cortex-R5F

On 05/03/2018 01:56 PM, Edgar E. Iglesias wrote: From: "Edgar E. Iglesias" Add the Cortex-R5F with the optional FPU enabled. Seems ok to me. Reviewed-by: KONRAD Frederic Signed-off-by: Edgar E. Iglesias

Re: [Qemu-devel] [PATCH] s390-ccw: force diag 308 subcode to unsigned long

On 05/02/2018 08:52 AM, Cornelia Huck wrote: We currently pass an integer as the subcode parameter. However, the upper bits of the register containing the subcode need to be 0, which is not guaranteed unless we explicitly specify the subcode to be an unsigned long value. Fixes: d046c51dad3

[Qemu-devel] [PATCH] sheepdog: Fix sd_co_create_opts() memory leaks

Both the option string for the 'redundancy' option and the SheepdogRedundancy object that is created accordingly could be leaked in error paths. This fixes the memory leaks. Reported by Coverity (CID 1390614 and 1390641). Signed-off-by: Kevin Wolf --- block/sheepdog.c | 4

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