[Qemu-devel] [RFC PATCH 11/12] qemu-img: add bitmap dump

Signed-off-by: John Snow --- qemu-img-cmds.hx | 6 ++ qemu-img.c | 185 +++ 2 files changed, 191 insertions(+) diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx index 2fe31893cf..d25f359f5a 100644 ---

[Qemu-devel] [RFC PATCH 00/12] qemu-img: add bitmap queries

Allow qemu-img to show information about bitmaps stored in qcow2 images. Add a 'bitmap' meta-command with 'dump' sub-command to retrieve a list of dirty regions in bitmaps stored in a qcow2 image. RFC: - I am not 1000% convinced the bm_list caching is perfectly safe, especially with respect to

[Qemu-devel] [PATCH 0/9] target/m68k: Convert to TranslatorOps

FYI, I've only tested this with linux-user-test-0.3 and our qemu coldfire testing kernel. r~ Richard Henderson (9): target/m68k: Use DISAS_NORETURN for exceptions target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN target/m68k: Remove DISAS_JUMP_NEXT as unused target/m68k: Use

[Qemu-devel] [PATCH v2 14/27] target/arm: squash FZ16 behaviour for conversions

From: Alex Bennée The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Signed-off-by: Alex Bennée

[Qemu-devel] [RFC PATCH 03/12] block/qcow2-bitmap: avoid adjusting bm->flags for RO bitmaps

Instead of always setting IN_USE, handle whether or not the bitmap is read-only instead of a two-loop pass. This will allow us to show the flags exactly as they appear for bitmaps in `qemu-img info`. Signed-off-by: John Snow --- block/qcow2-bitmap.c | 48

[Qemu-devel] [RFC PATCH 10/12] qemu-img: split off common chunk of map command

It will be re-used for a bitmap listing command. Signed-off-by: John Snow --- qemu-img.c | 192 +++-- 1 file changed, 110 insertions(+), 82 deletions(-) diff --git a/qemu-img.c b/qemu-img.c index ea62d2d61e..e31e38f674

[Qemu-devel] [RFC PATCH 07/12] qcow2-bitmap: add basic bitmaps info

Add functions for querying the basic information inside of bitmaps. Restructure the bitmaps flags masks to facilitate providing a list of flags belonging to the bitmap(s) being queried. Signed-off-by: John Snow --- block/qcow2-bitmap.c | 81

[Qemu-devel] [PATCH 6/9] target/m68k: Convert to DisasContextBase

Removed ctx->insn_pc in favour of ctx->base.pc_next. Yes, it is annoying, but didn't want to waste its 4 bytes. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 137 1 file changed, 67 insertions(+), 70

[Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN

We have exited the TB after using goto_tb; there is no distinction from DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/m68k/translate.c

[Qemu-devel] [PATCH 2/2] target/s390x: Fix brace Werror with clang 6.0.0

The warning is target/s390x/misc_helper.c:209:21: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] SysIB sysib = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per ISO C89,

[Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions

The raise_exception helper does not return. Do not generate any code following that. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m68k/translate.c

Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180512050250.12774-1-richard.hender...@linaro.org Subject: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps === TEST SCRIPT BEGIN === #!/bin/bash

[Qemu-devel] [PATCH v2 10/27] fpu/softfloat: re-factor float to float conversions

From: Alex Bennée This allows us to delete a lot of additional boilerplate code which is no longer needed. Currently the ieee flag is ignored (everything is assumed to be ieee). Handling for ARM AHP will be in the next patch. Signed-off-by: Alex Bennée

[Qemu-devel] [PATCH v2 22/27] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN

We have already checked the arguments for SNaN; we don't need to do it again. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 44 +- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git

[Qemu-devel] [PATCH v2 13/27] target/arm: convert conversion helpers to fpst/ahp_flag

From: Alex Bennée Instead of passing env and leaving it up to the helper to get the right fpstatus we pass it explicitly. There was already a get_fpstatus helper for neon for the 32 bit code. We also add an get_ahp_flag() for passing the state of the alternative FP16

[Qemu-devel] [PATCH v2 17/27] target/hppa: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 ---

[Qemu-devel] [PATCH v2 11/27] fpu/softfloat: support ARM Alternative half-precision

From: Alex Bennée For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. To support this I've added an additional FloatFmt (float16_params_ahp). The new FloatFmt flag

[Qemu-devel] [PATCH 2/2] target/s390x: Fix brace Werror with clang 6.0.0

The warning is target/s390x/misc_helper.c:209:21: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] SysIB sysib = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per ISO C89,

[Qemu-devel] [PATCH v2 26/27] fpu/softfloat: Pass FloatClass to pickNaN

For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 168 ++--- fpu/softfloat.c| 3 +- 2 files changed, 82 insertions(+), 89

[Qemu-devel] [PATCH v2 27/27] fpu/softfloat: Pass FloatClass to pickNaNMulAdd

For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 70 +++--- fpu/softfloat.c| 5 +-- 2 files changed, 28 insertions(+), 47

Re: [Qemu-devel] [PATCH RESEND v2] i386/kvm: add support for KVM_CAP_X86_DISABLE_EXITS

2018-05-12 5:57 GMT+08:00 Michael S. Tsirkin : > On Wed, Apr 18, 2018 at 09:09:19AM +0800, Wanpeng Li wrote: >> 2018-04-18 2:08 GMT+08:00 Michael S. Tsirkin : >> > On Tue, Apr 17, 2018 at 01:24:15AM -0700, Wanpeng Li wrote: >> >> From: Wanpeng Li

Re: [Qemu-devel] [PATCH 1/1] Fix conversion from uint64 to float128

On 05/11/2018 12:10 AM, Petr Tesarik wrote: > The significand is passed to normalizeRoundAndPackFloat128() as high > first, low second. The current code passes the integer first, so the > result is incorrectly shifted left by 64 bits. > > This bug affects the emulation of s390x instruction CXLGBR

[Qemu-devel] [RFC PATCH 01/12] qcow2-bitmap: cache bm_list

We don't need to re-read this list every time, exactly. We can keep it cached and delete our copy when we flush to disk. Because we don't try to flush bitmaps on close if there's nothing to flush, add a new conditional to delete the state anyway for a clean exit. Signed-off-by: John Snow

[Qemu-devel] [RFC PATCH 12/12] qemu-img: add bitmap clear

Signed-off-by: John Snow --- qemu-img-cmds.hx | 4 ++-- qemu-img.c | 46 -- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx index d25f359f5a..7b6ec73488 100644 ---

[Qemu-devel] [RFC PATCH 08/12] qjson: allow caller to ask for arbitrary indent

The function already exists, just expose it. Signed-off-by: John Snow --- include/qapi/qmp/qjson.h | 1 + qobject/qjson.c | 21 +++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/qapi/qmp/qjson.h b/include/qapi/qmp/qjson.h

[Qemu-devel] [RFC PATCH 05/12] qcow2-bitmap: track bitmap type

We only have one type of persistent bitmap right now, but I'd like the qemu-img tool to be able to give good diagnostic information if it sees an unknown/unsupported type. We do enforce it to be the dirty tracking type in check_dir_entry, but I wanted positive affirmation of the type in the

[Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6ab24fac0b..c795d8e64f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@

[Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP

These are all indirect or out-of-page direct jumps. We can indirectly chain to the next TB without going back to the main loop. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 7/9] target/m68k: Convert to TranslatorOps

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 176 1 file changed, 86 insertions(+), 90 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 01d3265437..0ab9ab1148 100644 ---

[Qemu-devel] [RFC PATCH 09/12] qapi/block-core: add BitmapMapping and BitmapEntry structs

Add two new structures for detailing the marked regions of bitmaps as saved in e.g. qcow2 files. Signed-off-by: John Snow --- qapi/block-core.json | 32 1 file changed, 32 insertions(+) diff --git a/qapi/block-core.json b/qapi/block-core.json

[Qemu-devel] [RFC PATCH 02/12] qcow2/dirty-bitmap: cache loaded bitmaps

For bitmaps that we succeeded in loading, we can cache a reference to that object. This will let us iterate over the more convenient form of in-memory bitmaps for qemu-img bitmap manipulation tools. Signed-off-by: John Snow --- block/qcow2-bitmap.c | 1 + 1 file changed, 1

[Qemu-devel] [RFC PATCH 04/12] qcow2/dirty-bitmaps: load IN_USE bitmaps if disk is RO

For the purposes of qemu-img manipulation and querying of bitmaps, load bitmaps that are "in use" -- if the image is read only. This will allow us to diagnose problems with this flag using the qemu-img tool. Signed-off-by: John Snow --- block/qcow2-bitmap.c | 32

[Qemu-devel] [RFC PATCH 06/12] qapi: add bitmap info

Add some of the necessary scaffolding for reporting bitmap information. Signed-off-by: John Snow --- qapi/block-core.json | 60 +++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/qapi/block-core.json

[Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP

These are all indirect or out-of-page direct jumps. We can indirectly chain to the next TB without going back to the main loop. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 5/9] target/m68k: Rename DISAS_UPDATE and gen_lookup_tb

The name gen_lookup_tb is at odds with tcg_gen_lookup_and_goto_tb. For these cases, we do indeed want to exit back to the main loop. Similarly, DISAS_UPDATE performs no actual update, whereas DISAS_EXIT does what it says. Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH 9/9] target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 069558bc28..21eeebf4df 100644 --- a/target/m68k/translate.c

[Qemu-devel] [PATCH v2 20/27] target/riscv: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code. Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v2 07/27] fpu/softfloat: Introduce parts_is_snan_frac

Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 15 +++ fpu/softfloat.c| 12 ++-- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index

[Qemu-devel] [PATCH v2 15/27] target/arm: Fix fp_status_f16 tininess before rounding

From: Peter Maydell In commit d81ce0ef2c4f105 we added an extra float_status field fp_status_fp16 for Arm, but forgot to initialize it correctly by setting it to float_tininess_before_rounding. This currently will only cause problems for the new V8_FP16 feature, since

[Qemu-devel] [PATCH v2 24/27] fpu/softfloat: Specialize on snan_bit_is_one

Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno Cc: Yongbok Kim Cc: David Gibson Cc: Alexander

[Qemu-devel] [PATCH v2 25/27] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h

We will need these helpers within softfloat-specialize.h, so move the definitions above the include. After specialization, they will not always be used so mark them to avoid the Werror. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30

Re: [Qemu-devel] [RFC PATCH 00/12] qemu-img: add bitmap queries

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180512012537.22478-1-js...@redhat.com Subject: [Qemu-devel] [RFC PATCH 00/12] qemu-img: add bitmap queries === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git

[Qemu-devel] [PATCH 1/2] hw/virtio: Fix brace Werror with clang 6.0.0

The warning is hw/virtio/vhost-user.c:1319:26: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] VhostUserMsg msg = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per

[Qemu-devel] [PATCH v2 21/27] target/s390x: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code. Cc: Alexander Graf Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/fpu_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6

[Qemu-devel] [PATCH v2 09/27] fpu/softfloat: Replace float_class_msnan with parts_silence_nan

With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 23 ++ fpu/softfloat.c| 40

[Qemu-devel] [PATCH v2 18/27] target/m68k: Use floatX_silence_nan when we have already checked for SNaN

Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index e41b07d042..6ec227e20f 100644

[Qemu-devel] [PATCH v2 23/27] fpu/softfloat: Remove floatX_maybe_silence_nan

These functions are now unused. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 63 -- include/fpu/softfloat.h| 5 --- 2 files changed, 68 deletions(-) diff --git a/fpu/softfloat-specialize.h

[Qemu-devel] [PATCH 1/2] hw/virtio: Fix brace Werror with clang 6.0.0

The warning is hw/virtio/vhost-user.c:1319:26: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] VhostUserMsg msg = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per

[Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions

The raise_exception helper does not return. Do not generate any code following that. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m68k/translate.c

[Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN

We have exited the TB after using goto_tb; there is no distinction from DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/m68k/translate.c

[Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps

[ Ho, hum. I didn't clear out my scratch directory before sending v1.0. ] FYI, I've only tested this with linux-user-test-0.3 and our qemu coldfire testing kernel. r~ Richard Henderson (9): target/m68k: Use DISAS_NORETURN for exceptions target/m68k: Replace DISAS_TB_JUMP with

[Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6ab24fac0b..c795d8e64f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@

[Qemu-devel] [PATCH 8/9] target/m68k: Improve ending TB at page boundaries

Rather than limit total TB size to PAGE-32 bytes, end the TB when near the end of a page. This should provide proper semantics of SIGSEGV when executing near the end of a page. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 22

[Qemu-devel] [PATCH v2 0/7] RISC-V: SoCify SiFive boards and connect GEM

This series has three tasks: 1. To convert the SiFive U and E machines into SoCs and boards 2. To connect the Cadence GEM device to the SiFive U board 3. Fix some device tree problems with the SiFive U board After this series the SiFive E and U boards have their SoCs split into seperate QEMU

[Qemu-devel] [PATCH v2 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs

Instead of creating the interrupt in lines with qemu_allocate_irq() use qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*() helpers later on. Signed-off-by: Alistair Francis Suggested-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCH v2 1/7] hw/riscv/sifive_u: Create a U54 SoC object

Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c

[Qemu-devel] [PATCH v2 2/7] hw/riscv/sifive_e: Create a E31 SoC object

Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 97 +++-- include/hw/riscv/sifive_e.h | 16 +- 2 files changed, 86 insertions(+), 27 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index

[Qemu-devel] [PATCH v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/

Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 50389cdc90..540d53bf2f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -194,7 +194,7

[Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts

Set the interrupt-controller ndev to the correct number taken from the HiFive Unleashed board. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index

[Qemu-devel] [PATCH v2 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus

To allow Linux to ennumerate devices on the /soc/ node set it as a "simple-bus". Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index

[Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

Connect the Cadence GEM ethernet device. This also requires us to expose the plic interrupt lines. Signed-off-by: Alistair Francis --- default-configs/riscv32-softmmu.mak | 1 + default-configs/riscv64-softmmu.mak | 1 + hw/riscv/sifive_u.c | 50

[Qemu-devel] [PATCH RFC v2 1/2] PC Chipset: Improve serial divisor calculation

This fixes several problems I found in the UART serial implementation. Now all divisor values are allowed, while before divisor values of zero and below the base baud rate were rejected. All changes are in reference to http://www.sci.muni.cz/docs/pc/serport.txt Signed-off-by: Calvin Lee

[Qemu-devel] [PATCH RFC v2 0/2] Fix UART serial implementation

Hello, While developing a serial implementation for my OS, I found several bugs in QEMU's serial device. I confirmed (by testing on my x64 laptop) that there are several inconsistancies between QEMU and hardware in this regard. For both patches, I used "http://www.sci.muni.cz/docs/pc/serport.txt;

[Qemu-devel] [PATCH RFC v2 2/2] PC Chipset: Send serial bytes at correct rate

This fixes bug in QEMU such that UART bytes would be sent immediatly after being put in the THR regardless of the UART frequency (and divisor). Now they will be sent at the appropriate rate. Signed-off-by: Calvin Lee --- I am not sure about VM migration here. I want to move a

[Qemu-devel] [PATCH v4 00/11] target/arm: Fixups for ARM_FEATURE_V8_FP16

Changes since v3: * Fixup rebase vs target-arm.next. One of the middle patches had conflicts resolved incorrectly, so the patch set was non-bisectable. Changes since v2: * Rebased vs target-arm.next. * Merged Peter's review. * Split out return fix as a separate patch. Changes

[Qemu-devel] [PATCH v4 02/11] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

No sense in emitting code after the exception. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5b8cf75e9f..11d8c07943

[Qemu-devel] [PATCH v4 07/11] target/arm: Implement FP data-processing (3 source) for fp16

We missed all of the scalar fp16 fma operations. Cc: qemu-sta...@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++ 1 file changed, 48

[Qemu-devel] [PATCH v4 03/11] target/arm: Implement FCVT (scalar, integer) for fp16

Cc: qemu-sta...@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h| 6 +++ target/arm/helper.c| 38 ++- target/arm/translate-a64.c | 96

[Qemu-devel] [PATCH v4 01/11] target/arm: Implement FMOV (general) for fp16

Adding the fp16 moves to/from general registers. Cc: qemu-sta...@nongnu.org Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 21 + 1 file changed, 21 insertions(+) diff --git a/target/arm/translate-a64.c

[Qemu-devel] [PATCH v4 08/11] target/arm: Implement FCMP for fp16

From: Alex Bennée These where missed out from the rest of the half-precision work. Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Diagnose lack of FP16 before fp_access_check]

[Qemu-devel] [PATCH v4 05/11] target/arm: Introduce and use read_fp_hreg

Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 30 ++ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git

[Qemu-devel] [PATCH v4 04/11] target/arm: Implement FCVT (scalar, fixed-point) for fp16

Cc: qemu-sta...@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c

[Qemu-devel] [PATCH v4 10/11] target/arm: Implement FMOV (immediate) for fp16

From: Alex Bennée All the hard work is already done by vfp_expand_imm, we just need to make sure we pick up the correct size. Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Merge

[Qemu-devel] [PATCH v4 06/11] target/arm: Implement FP data-processing (2 source) for fp16

We missed all of the scalar fp16 binary operations. Cc: qemu-sta...@nongnu.org Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++ 1 file changed, 65

[Qemu-devel] [PATCH v4 09/11] target/arm: Implement FCSEL for fp16

From: Alex Bennée These were missed out from the rest of the half-precision work. Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Alex Bennée [rth: Fix erroneous check vs type] Signed-off-by:

[Qemu-devel] [PATCH v2 03/27] fpu/softfloat: Merge NO_SIGNALING_NANS definitions

Move the ifdef inside the relevant functions instead of duplicating the function declarations. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 100 +++-- 1 file

[Qemu-devel] [PATCH v4 11/11] target/arm: Fix sqrt_f16 exception raising

From: Alex Bennée We are meant to explicitly pass fpst, not cpu_env. Cc: qemu-sta...@nongnu.org Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v2 00/27] softfloat patch roundup

This is my SNaN patch set, Alex's float-float refactor, and a couple of other random outstanding fpu patches. This has been reordered so as to be bisectable, since the float-float refactor requires the snan work to avoid breakage. It probably doesn't matter, but this was built on top of my arm

[Qemu-devel] [PATCH v2 01/27] fpu/softfloat: int_to_float ensure r fully initialised

From: Alex Bennée Reported by Coverity (CID1390635). We ensure this for uint_to_float later on so we might as well mirror that. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +-

[Qemu-devel] [PATCH v2 06/27] fpu/softfloat: Canonicalize NaN fraction

Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. Immediately, this simplifies the float-to-float conversion. Later, this will facilitate manipulation of NaNs within the shared code paths. Signed-off-by: Richard Henderson

[Qemu-devel] [PATCH v2 08/27] fpu/softfloat: Replace float_class_dnan with parts_default_nan

With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Note one case where we uselessly assigned to a.sign, which was overwritten/ignored later when expanding float_class_dnan. Signed-off-by: Richard

[Qemu-devel] [PATCH v2 12/27] target/arm: Use floatX_silence_nan when we have already checked for SNaN

Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4f8034c513..6f0eb83661 100644

[Qemu-devel] [PATCH v2 02/27] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

From: Peter Maydell In float-to-integer conversion, if the floating point input converts exactly to the largest or smallest integer that fits in to the result type, this is not an overflow. In this situation we were producing the correct result value, but were

[Qemu-devel] [PATCH v2 05/27] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition

We want to be able to specialize on the canonical representation. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git

[Qemu-devel] [PATCH v2 19/27] target/mips: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/msa_helper.c | 4 target/mips/op_helper.c | 2 -- 2 files changed, 6

[Qemu-devel] [PATCH v2 16/27] target/arm: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/target/arm/helper-a64.c

[Qemu-devel] [PATCH v2 04/27] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan

The new function assumes that the input is an SNaN and does not double-check. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 174 + include/fpu/softfloat.h|

[Qemu-devel] [PATCH 1/1] Fix conversion from uint64 to float128

The significand is passed to normalizeRoundAndPackFloat128() as high first, low second. The current code passes the integer first, so the result is incorrectly shifted left by 64 bits. This bug affects the emulation of s390x instruction CXLGBR (convert from logical 64-bit binary-integer operand

Re: [Qemu-devel] [PATCH 1/1] Fix conversion from uint64 to float128

On Fri, 11 May 2018 09:10:52 +0200 Petr Tesarik wrote: > The significand is passed to normalizeRoundAndPackFloat128() as high > first, low second. The current code passes the integer first, so the > result is incorrectly shifted left by 64 bits. > > This bug affects the

Re: [Qemu-devel] GSoC18: Cortex-M0 / micro:bit

On Fri, May 11, 2018 at 12:37 AM, Steffen Görtz wrote: > my name is Steffen. I am a master candidate in electrical engineering at > RWTH University in Aachen, Germany. > Together with Julia Suvorova i will work on Cortex-M0 / BBC micro:bit > support in QEMU this summer.

Re: [Qemu-devel] [PATCH 01/19] fpu/softfloat: Merge NO_SIGNALING_NANS definitions

Richard Henderson writes: > Move the ifdef inside the relevant functions instead of > duplicating the function declarations. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée > --- >

Re: [Qemu-devel] [PATCH 14/19] target/s390x: Remove floatX_maybe_silence_nan from conversions

On 11.05.2018 02:43, Richard Henderson wrote: > This is now handled properly by the generic softfloat code. > > Cc: Alexander Graf > Cc: David Hildenbrand > Signed-off-by: Richard Henderson > --- > target/s390x/fpu_helper.c | 12

[Qemu-devel] ping latency issue on passthrough guest

Hi all, I booted two sr-iov guests using KVM-VFIO and pinged each other with no-load one night. I found that most of the latency was little than 0.1ms, but several icmp_seq greater than 10ms, even up to 1000ms; root@test-ping01:~# grep "time=[0-9][0-9]" outputfile Mon May 7 23:05:12 201864

Re: [Qemu-devel] (resend)[PATCH 1/2] ps2: Clear the queue on PS/2 mouse reset and obey device disable

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180507123014.c67be381...@moya.office.hostfission.com Subject: [Qemu-devel] (resend)[PATCH 1/2] ps2: Clear the queue on PS/2 mouse reset and obey device disable === TEST

Re: [Qemu-devel] [RFC PATCH v2 00/19] reverse debugging

> From: Ciro Santilli [mailto:ciro.santi...@gmail.com] > Did you manage to reproduce and solve the savevm and loadvm problems I > mentioned at: > http://lists.nongnu.org/archive/html/qemu-devel/2018-04/msg05219.html > ? I've tried to debug your scenario and found a bug in saving/loading PS/2

Re: [Qemu-devel] [PATCH v3 2/9] raw: Implement copy offloading

On Wed, 05/09 10:17, Eric Blake wrote: > On 05/09/2018 09:58 AM, Fam Zheng wrote: > > Just pass down to ->file. > > > > Signed-off-by: Fam Zheng > > Reviewed-by: Stefan Hajnoczi > > --- > > block/raw-format.c | 20 > > 1 file

Re: [Qemu-devel] [PATCH v3] migration: discard non-migratable RAMBlocks

Hello David, Yesterday evening, I forgot to add the quote requested by Peter and to add the MIPS maintainers. Could you please add the paragraph below if the patch is accepted ? I think it's worth resending a v4 for that. Thanks, C. On 05/11/2018 12:02 AM, Cédric Le Goater wrote: > On the

Re: [Qemu-devel] [PATCH 1/9 V5] memory, exec: switch file ram allocation functions to 'flags' parameters

> >  >  > >Sent: Friday, May 11, 2018 at 5:08 AM >From: "Murilo Opsfelder Araujo" >To: junyan...@gmx.com >Cc: "Haozhong Zhang" , xiaoguangrong.e...@gmail.com, >crosthwaite.pe...@gmail.com, m...@redhat.com, qemu-devel@nongnu.org,

Re: [Qemu-devel] [PATCH v3 4/9] file-posix: Implement bdrv_co_copy_range

On Thu, 05/10 09:50, Stefan Hajnoczi wrote: > On Wed, May 09, 2018 at 10:58:10PM +0800, Fam Zheng wrote: > > +static off_t copy_file_range(int in_fd, off_t *in_off, int out_fd, > > + off_t *out_off, size_t len, unsigned int > > flags) > > +{ > > +#ifdef

Re: [Qemu-devel] [PATCH v1 0/8] MemoryDevice: introduce and use ResourceHandler

On 10.05.2018 15:32, Igor Mammedov wrote: > On Thu, 10 May 2018 15:20:55 +0200 > David Hildenbrand wrote: > >> On 10.05.2018 15:02, Igor Mammedov wrote: >>> On Wed, 9 May 2018 16:13:14 +0200 >>> David Hildenbrand wrote: >>> On 03.05.2018 17:49, David

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