From: Richard Henderson
This allows faults from MO_ALIGN to have the same effect
as from gen_check_align.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/excp_helper.c| 18 +-
target/ppc/internal.h | 5 +
From: Cédric Le Goater
This makes possible to move the common ICSState code of the realize
handlers in the ics-base class.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c| 37 ++---
hw/intc/xics_kvm.c| 20
From: Richard Henderson
Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations
instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an
explicit call to gen_check_align.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c |
From: Cédric Le Goater
Just like for the realize handlers, this makes possible to move the
common ICSState code of the reset handlers in the ics-base class.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c| 45 ---
From: Richard Henderson
These operations were previously unimplemented for ppc.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c
At present the Sam460ex board is activated by the general CONFIG_PPC4XX
option. However that includes the board for both ppc-softmmu and
(deprecated) ppcemb-softmmu builds. As Sam460ex is developed, that would
require adding more things into ppcemb-softmmu, which we don't want to do.
From: "Emilio G. Cota"
The use of GDB breakpoints was broken by b0c2d52 ("target/ppc: convert
to TranslatorOps", 2018-02-16).
Fix it by setting is_jmp, so that we break from the translation loop
as originally intended.
Tested-by: Mark Cave-Ayland
Reported-by: Mark Cave-Ayland
Signed-off-by:
From: BALATON Zoltan
Rewrite to make it closer to how real device works so that guest OS
drivers can access I2C devices. Previously this was only a hack to
allow U-Boot to get past accessing SPD EEPROMs but to support other
I2C devices and allow guests to access them we need to model real
device
From: Sebastian Bauer
Drivers for this card exists on PPC-based AmigaOS guests so it is useful to
allow users to emulate the graphics card for PPC machines.
As cirrus vga is currently preferred over std(vga) in absence of any user
choice, this change also sets the default display of spapr
Eric Blake writes:
> On 07/02/2018 11:21 AM, Markus Armbruster wrote:
>> tests/qmp-test tests an out-of-band command overtaking a slow in-band
>> command. To do that, it needs:
>>
>> 1. An in-band command that *reliably* takes long enough to be
>> overtaken.
>>
>> 2. An out-of-band command
On Tue, Jul 03, 2018 at 08:14:35AM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > On Mon, Jul 02, 2018 at 06:21:53PM +0200, Markus Armbruster wrote:
> >> Commit cf869d53172 "qmp: support out-of-band (oob) execution" made
> >> "id" mandatory for all commands when the client accepted
On 06/29/2018 07:22 PM, Dr. David Alan Gilbert wrote:
* Xiao Guangrong (guangrong.x...@gmail.com) wrote:
On 06/19/2018 03:36 PM, Peter Xu wrote:
On Mon, Jun 04, 2018 at 05:55:15PM +0800, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
Try to hold src_page_req_mutex only if the
Eric Blake writes:
> On 07/02/2018 11:22 AM, Markus Armbruster wrote:
>> monitor_qmp_dispatch_one() frees a QMPRequest manually, because it
>> needs to keep a reference to ->id. Premature optimization. Take an
>> additional reference so we can use qmp_request_free().
>>
>> Signed-off-by:
On Mon, Jul 02, 2018 at 02:03:58PM -0300, Philippe Mathieu-Daudé wrote:
> On 07/02/2018 01:43 PM, Gerd Hoffmann wrote:
> > On Mon, Jul 02, 2018 at 06:33:45PM +0200, Gerd Hoffmann wrote:
> >> Two vga cards will try to register for the same legacy (isa) ioports.
> >> Due to this conflict only one of
Eric Blake writes:
> On 07/02/2018 11:22 AM, Markus Armbruster wrote:
>> qmp_greeting() offers capabilities to the client, and
>> qmp_qmp_capabilities() accepts or denies capabilities requested by the
>> client. The two compute the set of available capabilities
>> independently. Not nice.
>>
Peter Xu writes:
> On Mon, Jul 02, 2018 at 06:22:02PM +0200, Markus Armbruster wrote:
>> When OOB is enabled, out-of-band commands are executed right away,
>> everything else is queued. This lets out-of-band commands "jump the
>> queue".
>>
>> However, certain errors are always reported right
From: BALATON Zoltan
Basic emulation of the M41T80 serial (I2C) RTC chip. Only getting time
of day is implemented. Setting time and RTC alarm are not supported.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
MAINTAINERS | 1
From: Cédric Le Goater
This changes the ICP realize and reset handlers in DeviceRealize and
DeviceReset handlers. parent handlers are now called from the
inheriting classes which is a cleaner object pattern.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c
From: Greg Kurz
In a future patch the machine code will need to retrieve the MMU
information from KVM during machine initialization before the CPUs
are created.
Actually, KVM_PPC_GET_SMMU_INFO is a VM class ioctl, and thus, we
don't need to have a CPU object around. We just need for KVM to
be
From: Greg Kurz
Now that we're checking our MMU configuration is supported by KVM,
rather than adjusting it to KVM, it doesn't really make sense to
have a fallback for kvm_get_smmu_info(). If KVM is too old or buggy
to provide the details, we should rather treat this as an error.
This patch
From: BALATON Zoltan
PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
can get further booting on the sam460ex machine.
Signed-off-by: BALATON Zoltan
Signed-off-by: David Gibson
---
hw/ppc/ppc440.h
On Mon, Jul 02, 2018 at 06:22:02PM +0200, Markus Armbruster wrote:
> When OOB is enabled, out-of-band commands are executed right away,
> everything else is queued. This lets out-of-band commands "jump the
> queue".
>
> However, certain errors are always reported right away, and therefore
> can
Eric Blake writes:
> On 07/02/2018 11:21 AM, Markus Armbruster wrote:
>> Commit cf869d53172 "qmp: support out-of-band (oob) execution" made
>> "id" mandatory for all commands when the client accepted capability
>> "oob". This is rather onerous when you play with QMP by hand, and
>>
Eric Blake writes:
> On 07/02/2018 11:22 AM, Markus Armbruster wrote:
>> handle_qmp_command() reports certain errors right away. This is wrong
>> when OOB is enabled, because the errors can "jump the queue" then, as
>> the previous commit demonstrates.
>>
>> To fix, we need to delay errors
Peter Xu writes:
> On Mon, Jul 02, 2018 at 06:21:46PM +0200, Markus Armbruster wrote:
>> We're trying to get the out-of-band execution feature ready. This
>> series fixes a number of issues, and marks a design flaw FIXME. More
>> work is needed.
>
> Hi, Markus,
>
> I roughly went over the
From: Richard Henderson
Section 1.4 of the Power ISA v3.0B states that both of these
instructions are single-copy atomic. As we cannot (yet) issue
128-bit loads within TCG, use the generic helpers provided.
Since TCG cannot (yet) return a 128-bit value, add a slot within
CPUPPCState for
From: Cédric Le Goater
With the previous changes, we can now let the ICS_KVM class inherit
directly from ICS_BASE class and not from the intermediate ICS_SIMPLE.
It makes the class hierarchy much cleaner.
What is left in the top classes is the low level interface to access
the KVM XICS device
From: Guenter Roeck
sam460ex (or at least this emulation) does not support the "ibm,cpm" power
management. As a result, Linux crashes when trying to access it. Remove
its device tree node. Also, if/when we boot the Linux kernel directly,
serial port clock frequencies in the device tree file will
From: Richard Henderson
This avoids the need for gen_check_align entirely.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target/ppc/translate.c
From: Richard Henderson
These cases were stubbed out. For now, implement them only within
a serial context, forcing parallel execution to synchronize. It
would be possible to implement these with cmpxchg loops, if we care.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
From: Richard Henderson
Leave only the minimal amount of code within the STCX macro,
moving the rest of the code into gen_conditional_store.
Remove the explicit call to gen_check_align; the matching LDAX will
have already checked alignment, and we verify the same address.
Signed-off-by: Richard
From: Mark Cave-Ayland
Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a
workaround for MacOS 9 incorrectly setting the mouse address during boot of
PMU machines.
Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte
ordering" this can still
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index d6066d561f..83340770f7 100644
--- a/hw/intc/xics.c
+++
From: Richard Henderson
The store twin case was stubbed out. For now, implement it only within
a serial context, forcing parallel execution to synchronize. It would
be possible to implement with a cmpxchg loop, if we care, but the loose
alignment requirements (simply no crossing 32-byte
From: Richard Henderson
When running in a parallel context, we must use a helper in order
to perform the 128-bit atomic operation. When running in a serial
context, do the compare before the store.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/helper.h | 2
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/intc/xics.c | 112 -
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 8cfe223153..b9f1a3c972 100644
From: BALATON Zoltan
The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
From: Richard Henderson
Section 1.4 of the Power ISA v3.0B states that this insn is
single-copy atomic. As we cannot (yet) issue 128-bit stores
within TCG, use the generic helpers provided.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/helper.h | 4
From: Greg Kurz
It is currently not possible to run a pseries-2.12 or older machine
with HV KVM. QEMU prints the following and exits right away.
qemu-system-ppc64: KVM doesn't support for base page shift 34
The "hpt-max-page-size" capability was recently added to spapr to hide
host
From: Richard Henderson
Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations
instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an
explicit call to gen_check_align.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
target/ppc/translate.c |
From: Richard Henderson
Always use the gen_conditional_store implementation that uses
atomic_cmpxchg. Make sure and clear reserve_addr across most
interrupts crossing the cpu_loop.
Signed-off-by: Richard Henderson
Signed-off-by: David Gibson
---
linux-user/ppc/cpu_loop.c | 121
Eric Blake writes:
> On 07/02/2018 11:21 AM, Markus Armbruster wrote:
>> OOB documentation is spread over qmp-spec.txt sections 2.2.1
>> Capabilities and 2.3 Issuing Commands. The amount of detail is a bit
>> distracting there. Move the meat of the matter to new section 2.3.1
>> Out of band
From: BALATON Zoltan
The Sam460ex has an M41T80 serial RTC chip on I2C bus 0 at address 0x68.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/sam460ex.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/sam460ex.c
From: John Arbuckle
The FPSCR[FI] bit indicates if the last floating point instruction had a result
that was rounded. Each consecutive floating point instruction is suppose to set
this bit to the correct value. What currently happens is this bit is not set as
often as it should be. I have
Peter Xu writes:
> On Mon, Jul 02, 2018 at 06:21:53PM +0200, Markus Armbruster wrote:
>> Commit cf869d53172 "qmp: support out-of-band (oob) execution" made
>> "id" mandatory for all commands when the client accepted capability
>> "oob". This is rather onerous when you play with QMP by hand, and
Eric Blake writes:
> On 07/02/2018 11:21 AM, Markus Armbruster wrote:
>> Signed-off-by: Markus Armbruster
>> ---
>> tests/test-qga.c | 17 +
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/tests/test-qga.c b/tests/test-qga.c
>> index 30c9643257..4edd35535d 100644
>>
On Mon, Jul 02, 2018 at 06:21:46PM +0200, Markus Armbruster wrote:
> We're trying to get the out-of-band execution feature ready. This
> series fixes a number of issues, and marks a design flaw FIXME. More
> work is needed.
Hi, Markus,
I roughly went over the series (without going into every
Eric Blake writes:
> On 07/02/2018 11:21 AM, Markus Armbruster wrote:
>> Signed-off-by: Markus Armbruster
>> ---
>> tests/test-qga.c | 17 +
>> 1 file changed, 17 insertions(+)
>
> Well, if we get rid of 'control' in favor of 'exec-oob', this test
> would still have to test
Hi
On Mon, Jul 2, 2018 at 6:21 PM, Markus Armbruster wrote:
> We're trying to get the out-of-band execution feature ready. This
> series fixes a number of issues, and marks a design flaw FIXME. More
> work is needed.
They are several related worthy cleanups in the qapi-async series.
They
From: Shameer Kolothum
This patch adds the the memory hot-plug/hot-unplug infrastructure
in machvirt.
Signed-off-by: Eric Auger
Signed-off-by: Shameer Kolothum
Signed-off-by: Kwangwoo Lee
---
v1 -> v2:
- s/virt_dimm_plug|unplug/virt_memory_plug|unplug
- s/pc_dimm_memory_plug/pc_dimm_plug
-
On 06/29/2018 09:08 PM, Michael S. Tsirkin wrote:
On Fri, Jun 29, 2018 at 03:30:44PM +0800, Xiao Guangrong wrote:
Hi Michael,
On 06/20/2018 08:38 PM, Michael S. Tsirkin wrote:
On Mon, Jun 04, 2018 at 05:55:17PM +0800, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
(1)
The kvm-type property currently is used to pass
a user parameter to KVM_CREATE_VM. This matches
the way KVM/ARM expects to pass the max_vm_phys_shift
parameter.
This patch adds the support or the kvm-type property in
machvirt and also implements the machine class kvm_type()
callback so that it
We plan to reuse build_srat_hotpluggable_memory() for ARM so
let's move the function to aml-build.
Signed-off-by: Eric Auger
---
hw/acpi/aml-build.c | 51 +
hw/i386/acpi-build.c| 49 ---
This is a header update against
git://linux-arm.org/linux-skp.git ipa52/v3
to get the KVM_ARM_GET_MAX_VM_PHYS_SHIFT ioctl. This allows to retrieve
the IPA address range KVM supports.
Signed-off-by: Eric Auger
---
include/standard-headers/linux/virtio_config.h | 16
Add the kvm_arm_get_max_vm_phys_shift() helper that returns the
log of the maximum IPA size supported by KVM. This capability
needs to be known to create the VM with a correct IPA max size
(kvm_type passed along KVM_CREATE_VM ioctl.
Signed-off-by: Eric Auger
---
v1 -> v2:
- put this in ARM
On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo
>
> Based on kernel commit 1eaafe91, it looks like
On Mon, Jul 02, 2018 at 03:55:33PM -0500, Eric Blake wrote:
> On 07/02/2018 11:58 AM, Roman Kagan wrote:
> > This series modifies the management of HvSintRoute, which is an
> > important building block in Hyper-V emulation infrastructure, to make it
> > easier to maintain and enhance, and paves
Hi Dan, I was on holiday yesterday so I guess we've missed the deadline.
In any case I will post v6 with the requested change in a few minutes.
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog:
On Tue, 07/03 10:47, Roman Kagan wrote:
> On Mon, Jul 02, 2018 at 03:55:33PM -0500, Eric Blake wrote:
> > On 07/02/2018 11:58 AM, Roman Kagan wrote:
> > > This series modifies the management of HvSintRoute, which is an
> > > important building block in Hyper-V emulation infrastructure, to make it
Pre-Shared Keys (PSK) is a simpler mechanism for enabling TLS
connections than using certificates. It requires only a simple secret
key:
$ mkdir -m 0700 /tmp/keys
$ psktool -u rjones -p /tmp/keys/keys.psk
$ cat /tmp/keys/keys.psk
v5 was here:
https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg08491.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00077.html
v6:
- Make ECDHE-PSK dependent on GnuTLS >= 3.
- Retested against nbdkit.
- Retested with internal unit tests.
Rich.
Hi Michael,
On 06/29/2018 06:42 PM, Michael S. Tsirkin wrote:
On Fri, Jun 29, 2018 at 12:15:21PM +0100, Suzuki K Poulose wrote:
virtio-mmio with virtio-v1 uses a 32bit PFN for the queue.
If the queue pfn is too large to fit in 32bits, which
we could hit on arm64 systems with 52bit physical
Hi David,
On 07/02/2018 11:37 AM, David Hildenbrand wrote:
> Let's set the alignment just like for the posix variant. This will
> implicitly set the alignment of the underlying memory region and
> therefore make memory_region_get_alignment(mr) return something > 0 for
> all memory backends
Hi David,
On 07/02/2018 02:47 PM, David Hildenbrand wrote:
> On 02.07.2018 14:44, Igor Mammedov wrote:
>> On Mon, 2 Jul 2018 12:39:43 +0200
>> David Hildenbrand wrote:
>>
>>> On 02.07.2018 12:31, Igor Mammedov wrote:
On Mon, 2 Jul 2018 11:37:55 +0200
David Hildenbrand wrote:
Hi David,
On 07/02/2018 02:47 PM, David Hildenbrand wrote:
> On 02.07.2018 14:44, Igor Mammedov wrote:
>> On Mon, 2 Jul 2018 12:39:43 +0200
>> David Hildenbrand wrote:
>>
>>> On 02.07.2018 12:31, Igor Mammedov wrote:
On Mon, 2 Jul 2018 11:37:55 +0200
David Hildenbrand wrote:
From: Sebastian Bauer
Fetching qtd with the NULL address most likely makes no sense so from now
on, we handle it this case similarly as if the terminate (T) bit is not
set, which is already an exception as according to section 3.6 of the EHCI
spec there is no T bit defined for the current_qtd
The following changes since commit ab08440a4ee09032d1a9cb22fdcab23bc7e1c656:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180702' into
staging (2018-07-02 17:57:46 +0100)
are available in the git repository at:
git://git.kraxel.org/qemu tags/usb-20180703-pull-request
for you
Set xhci into error state instead of throwing a core dump.
Signed-off-by: Gerd Hoffmann
Message-id: 20180702162752.29233-1-kra...@redhat.com
---
hw/usb/hcd-xhci.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index
Report total file system size and free space in output of command
"guest-get-fsinfo". Values are optional and it is not an error if they cannot
be retrieved for some reason.
Signed-off-by: Tomáš Golembiovský
---
qga/commands-posix.c | 18 ++
qga/commands-win32.c | 16
Marc-André Lureau writes:
> Hi
>
> On Mon, Jul 2, 2018 at 6:21 PM, Markus Armbruster wrote:
>> We're trying to get the out-of-band execution feature ready. This
>> series fixes a number of issues, and marks a design flaw FIXME. More
>> work is needed.
>
> They are several related worthy
On 3 July 2018 at 09:00, Greg Kurz wrote:
> On Mon, 2 Jul 2018 18:31:25 +0200
> Paolo Bonzini wrote:
>
>> hw/9pfs/Makefile.objs uses CONFIG_VIRTIO_9P to guard the definition for
>> FileOperations structs, while fsdev/Makefile.objs uses CONFIG_VIRTIO
>> to guard the use. Mismatch causes linking
On Thu, 2018-06-28 at 16:20 +0200, Paolo Bonzini wrote:
> On 28/06/2018 11:25, Robert Hoo wrote:
> >>> +uint64_t pred_cmd;
> >>> +uint64_t arch_capabilities;
> >> What's the purpose of those CPUX86State fields, if the migration
> >> sections were removed in v2?
> >>
> > Thanks Eduardo.
On 2 July 2018 at 16:45, Paolo Bonzini wrote:
> The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
>
> tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
>
> are available in the git repository at:
>
> git://github.com/bonzini/qemu.git
> /usr/bin/strace: ptrace(PTRACE_TRACEME, ...): Function not implemented
This indicates that you're trying to run an x86 strace under QEMU. That
won't work. You want to either (a) run QEMU + guest binary under the
host strace or (b) run QEMU + guest binary with the QEMU -strace option.
--
You
In record/replay icount mode vCPU thread and iothread synchronize
the execution using the checkpoints.
vCPU thread processes the virtual timers and iothread processes all others.
When iothread wants to wake up sleeping vCPU thread, it sends dummy queued
work. Therefore it could be the following
OOB documentation is spread over qmp-spec.txt sections 2.2.1
Capabilities and 2.3 Issuing Commands. The amount of detail is a bit
distracting there. Move the meat of the matter to new section 2.3.1
Out of band execution.
Throw in a few other improvements while there:
* 2.2 Server Greeting:
When OOB is enabled, out-of-band commands are executed right away,
everything else is queued. This lets out-of-band commands "jump the
queue".
However, certain errors are always reported right away, and therefore
can jump the queue even when the erroneous input does not request
out-of-band
Commit 71da4667db6 "monitor: separate QMP parser and dispatcher" moved
the handle_qmp_command tracepoint from handle_qmp_command() to
monitor_qmp_dispatch_one(). This delays tracing from enqueue time to
dequeue time. Revert that. Dequeue remains adequately visible via
tracepoint
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
tests/test-qga.c | 20
1 file changed, 20 insertions(+)
diff --git a/tests/test-qga.c b/tests/test-qga.c
index 30c9643257..6b632e3da4 100644
--- a/tests/test-qga.c
+++ b/tests/test-qga.c
@@ -227,6 +227,25 @@
tests/qmp-test tests an out-of-band command overtaking a slow in-band
command. To do that, it needs:
1. An in-band command that *reliably* takes long enough to be
overtaken.
2. An out-of-band command to do the overtaking.
3. To avoid delays, a way to make the in-band command complete
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
tests/test-qga.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/tests/test-qga.c b/tests/test-qga.c
index 564a4594b5..2e9e0f73bb 100644
--- a/tests/test-qga.c
+++ b/tests/test-qga.c
@@ -243,6 +243,22 @@ static
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
tests/qmp-test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qmp-test.c b/tests/qmp-test.c
index 6dd331fcdd..d73730945a 100644
--- a/tests/qmp-test.c
+++ b/tests/qmp-test.c
@@ -239,10 +239,12 @@ static void
There's just one use of qobject_from_jsonf() to parse a JSON object
left: timestamp_put(). Switch it to qdict_from_jsonf_nofail().
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
qapi/qmp-event.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
Change monitor_qmp_dispatch_one() to take its parameters unwrapped,
move monitor_resume() to the one caller that needs it, rename the
function to monitor_qmp_dispatch().
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
monitor.c | 58
Affects documentation and a few error messages.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
docs/devel/qapi-code-gen.txt| 2 +-
docs/interop/qmp-spec.txt | 2 +-
monitor.c | 14 +++---
qapi/misc.json
We define a new hotpluggable RAM region (aka. device memory).
Its base is 2TB GPA. This obviously requires 42b IPA support
in KVM/ARM, FW and guest kernel. At the moment the device
memory region is max 2TB.
This is largely inspired of device memory initialization in
pc machine code.
From: Shameer Kolothum
We introduce an helper to create a memory node.
Signed-off-by: Eric Auger
Signed-off-by: Shameer Kolothum
---
v1 -> v2:
- nop of existing /memory nodes was already handled
---
hw/arm/boot.c | 54 ++
1 file changed,
From: Shameer Kolothum
Generate Memory Affinity Structures for PC-DIMM ranges.
Signed-off-by: Shameer Kolothum
Signed-off-by: Eric Auger
---
v1 -> v2:
- build_srat_hotpluggable_memory movedc to aml-build
---
hw/arm/virt-acpi-build.c | 4
1 file changed, 4 insertions(+)
diff --git
On ARM, the kvm_type will be resolved by querying the KVMState.
Let's add the MachineState handle to the callback so that we
can retrieve the KVMState handle. in kvm_init, when the callback
is called, the kvm_state variable is not yet set.
Signed-off-by: Eric Auger
Acked-by: David Gibson
[ppc
When migrating a VM, we must make sure the destination host
supports as many IPA bits as the source. Otherwise the migration
must fail.
We add a VMState infrastructure to machvirt. On pre_save(),
the current source max_vm_phys_shift is saved.
On destination, we cannot use this information when
This series aims at supporting PCDIMM/NVDIMM intantiation in
machvirt at 2TB guest physical address.
This is achieved in 3 steps:
1) support more than 40b IPA/GPA
2) support PCDIMM instantiation
3) support NVDIMM instantiation
This series reuses/rebases patches initially submitted by Shameer in
From: Kwangwoo Lee
Pre-plug and plug handlers are prepared for NVDIMM support.
Signed-off-by: Eric Auger
Signed-off-by: Kwangwoo Lee
---
default-configs/arm-softmmu.mak | 2 ++
hw/arm/virt-acpi-build.c| 6 ++
hw/arm/virt.c | 23 +++
The disk missing due to calling scsi_probe_lun failed in guest. The
guest code is below:
static int scsi_probe_lun(struct scsi_device *sdev, unsigned char
*inq_result,
int result_len, int *bflags)
{
.
result = scsi_execute_req(sdev, scsi_cmd, DMA_FROM_DEVICE,
In case of NV-DIMM slots, let's add /pmem DT nodes.
Signed-off-by: Eric Auger
---
hw/arm/boot.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 2c7d558..3381c66 100644
--- a/hw/arm/boot.c
+++
From: Shameer Kolothum
This patch add memory nodes corresponding to PC-DIMM regions.
NV_DIMM and ACPI_NVDIMM configs are not yet set for ARM so we
don't need to care about NV-DIMM at this stage.
Signed-off-by: Shameer Kolothum
Signed-off-by: Eric Auger
---
v1 -> v2:
- added
From: Kwangwoo Lee
This patch uses configurable IO base and size to create NPIO AML for
ACPI NFIT. Since a different architecture like AArch64 does not use
port-mapped IO, a configurable IO base is required to create correct
mapping of ACPI IO address and size.
Signed-off-by: Kwangwoo Lee
Machine option nvdimm allows to turn NVDIMM support on.
Signed-off-by: Eric Auger
---
hw/arm/virt.c | 60 ---
1 file changed, 57 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 51f42cd..13e6dec 100644
---
From: Junyan He
When QEMU emulates vNVDIMM labels and migrates vNVDIMM devices, it
needs to know whether the backend storage is a real persistent memory,
in order to decide whether special operations should be performed to
ensure the data persistence.
This boolean option 'pmem' allows users to
On Mon, 2 Jul 2018 18:31:25 +0200
Paolo Bonzini wrote:
> hw/9pfs/Makefile.objs uses CONFIG_VIRTIO_9P to guard the definition for
> FileOperations structs, while fsdev/Makefile.objs uses CONFIG_VIRTIO
> to guard the use. Mismatch causes linking to fail when CONFIG_VIRTIO
> is set but
Hi David,
On 07/02/2018 11:37 AM, David Hildenbrand wrote:
> All applicable memory regions always have an alignment > 0. All memory
> backends result in file_ram_alloc() or qemu_anon_ram_alloc() getting
> called, setting the alignment to > 0.
>
> So a PCDIMM memory region always has an alignment
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