On 9/6/19 3:57 AM, David Hildenbrand wrote:
> We can process a maximum of 256 bytes, crossing two pages.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/mem_helper.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/11/19 10:09 AM, Vladimir Sementsov-Ogievskiy wrote:
> 10.09.2019 23:37, no-re...@patchew.org wrote:
>> Patchew URL:
>> https://patchew.org/QEMU/20190910162724.79574-1-vsement...@virtuozzo.com/
>>
>>
>>
>> Hi,
>>
>> This series failed the docker-quick@centos7 build test. Please find the
>>
On 9/6/19 3:57 AM, David Hildenbrand wrote:
> +/*
> + * Our access should not exceed single pages, as we must not report
> access
> + * exceptions exceeding the actually copied range (which we don't know at
> + * this point). We might over-indicate watchpoints within the pages
> +
On 9/6/19 3:57 AM, David Hildenbrand wrote:
> +static void access_memmove_idx(CPUS390XState *env, vaddr dest, vaddr src,
> + int size, int dest_idx, int src_idx,
> + uintptr_t ra)
> +{
> +S390Access srca = access_prepare_idx(env, src,
On 9/11/19 4:33 PM, Eric Blake wrote:
> I tried to test this patch, but even with it applied, I still got an
> aio-context crasher by attempting an nbd-server-start, nbd-server-add,
> nbd-server-stop (intentionally skipping the nbd-server-remove step) on a
> domain using iothreads, with a backtrac
The 'blockdev-create' QMP command was introduced as experimental
feature in commit b0292b851b8, using the assert() debug call.
It got promoted to 'stable' command in 3fb588a0f2c, but the
assert call was not removed.
Some block drivers are optional, and bdrv_find_format() might
return a NULL value,
On 9/6/19 3:57 AM, David Hildenbrand wrote:
> Each operand can have a maximum length of 16. Make sure to prepare all
> reads/writes before writing.
>
> Signed-off-by: David Hildenbrand
> ---
> target/s390x/mem_helper.c | 26 ++
> 1 file changed, 14 insertions(+), 12 delet
On 9/11/19 5:08 PM, Philippe Mathieu-Daudé wrote:
> The 'blockdev-create' QMP command was introduced as experimental
> feature in commit b0292b851b8, using the assert() debug call.
> It got promoted to 'stable' command in 3fb588a0f2c, but the
> assert call was not removed.
>
> Some block drivers a
Public bug reported:
On gcc123 cfarm machine,
I was testing m68k executables generated by Free Pascal Compiler.
muller@gcc123:~/pas/check$ cat inf.pp
function get_double(x : double):double;
begin
get_double:=x;
end;
var
y : double;
py : pbyte;
i : byte;
begin
y:=1.0/0.0;
py:=@
On 9/11/19 2:25 AM, liuzhiwei wrote:
> uint64_t fpr[32]; /* assume both F and D extensions */
> +
> +/* vector coprocessor state. */
> +struct {
> +union VECTOR {
> +float64 f64[VUNIT(64)];
> +float32 f32[VUNIT(32)];
> +float16 f16[VUNIT(
On 9/11/19 10:51 AM, Chih-Min Chao wrote:
> Could the VLEN be configurable in cpu initialization but not fixed in
> compilation phase ?
> Take the integer element as example and the difference should be the
> stride of vfp.vreg[x] isn't continuous
Do you really want an unbounded amount of vector
On 9/11/19 2:25 AM, liuzhiwei wrote:
> @@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_FFLAGS] = { fs, read_fflags, write_fflags
> },
> [CSR_FRM] = { fs, read_frm, write_frm
> },
> [CSR_F
On 9/11/19 6:08 PM, Philippe Mathieu-Daudé wrote:
> The 'blockdev-create' QMP command was introduced as experimental
> feature in commit b0292b851b8, using the assert() debug call.
> It got promoted to 'stable' command in 3fb588a0f2c, but the
> assert call was not removed.
>
> Some block driver
> +void VECTOR_HELPER(vsetvl)(CPURISCVState *env, uint32_t rs1, uint32_t rs2,
> +uint32_t rd)
> +{
> +int sew, max_sew, vlmax, vl;
> +
> +if (rs2 == 0) {
> +vector_vtype_set_ill(env);
> +riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> +return;
> +
On 9/10/19 9:27 AM, Mark Syms wrote:
> Hi,
>
> While trying to track down an issue in using qemu 4.1 with some development
> features we needed/wanted to run valgrind on it to find a memory error.
> Unfortunately the form of the queue macros seems to really confuse valgrind
> and cause it to
On 9/11/19 11:16 AM, Alberto Garcia wrote:
> handle_alloc() tries to find as many contiguous clusters that need
> copy-on-write as possible in order to allocate all of them at the same
> time.
>
> However, compressed clusters are only overwritten one by one, so let's
> say that we have an image
On Wed, Sep 11, 2019 at 07:59:25PM +0530, Balamuruhan S wrote:
> There were few trailing comments after `/*` instead in
> new line and line more than 80 character, these fixes are
> trivial and doesn't change any logic in code.
>
> Signed-off-by: Balamuruhan S
This makes sense independent of the
This series uses python logging to enable output conditionally on
iotests.log(). We unify an initialization call (which also enables
debugging output for those tests with -d) and then make the switch
inside of iotests.
It will help alleviate the need to create logged/unlogged versions
of all the v
Switch from verify_protocols to any one of:
iotests.main, iotests.script_main, iotests.script_initialize.
Signed-off-by: John Snow
---
tests/qemu-iotests/207 | 4 ++--
tests/qemu-iotests/210 | 4 ++--
tests/qemu-iotests/211 | 4 ++--
tests/qemu-iotests/212 | 4 ++--
tests/qemu-iotests/213 | 4 ++
Like script_main, but doesn't require a single point of entry.
Replace all existing initialization sections with this drop-in replacement.
This brings debug support to all existing script-style iotests.
Note: supported_oses=['linux'] was omitted, as it is a default argument.
Signed-off-by: John S
On Wed, Sep 11, 2019 at 03:58:14PM +, Muolo Vincenzo (S.I.) wrote:
> Hi to all
>
> I try to use ( into VM debian 10 running into VMWARE virtualization
> environment ) qemu ppc64 version to simulate an AIX 7.1 TL04 OS
>
>
> root@vkvm-acmm:/AIX# qemu-system-ppc64 -version
> QEMU emulator
Since this one is nicely factored to use a single entry point,
use script_main to run the tests.
Signed-off-by: John Snow
---
tests/qemu-iotests/258 | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tests/qemu-iotests/258 b/tests/qemu-iotests/258
index b84cf02254..13725
We can turn logging on/off globally instead of per-function.
Remove use_log from run_job, and use python logging to turn on
diffable output when we run through a script entry point.
iotest 245 changes output order due to buffering reasons.
Signed-off-by: John Snow
---
tests/qemu-iotests/030
The following changes since commit 0d0b906ae20d763db0f07fc74aef2c355b8474c7:
spapr: Render full FDT on ibm,client-architecture-support (2019-09-11
16:22:29 +1000)
are available in the Git repository at:
g...@github.com:aik/qemu.git tags/qemu-slof-20190911
for you to fetch changes up to
Fedora23 is but a distant twinkle.
The sanitizer works again, and even if not,
we have --enable-sanitizers now.
---
The problem is that I do see some ASAN warnings:
TESTcheck-qtest-aarch64: tests/device-introspect-test
Direct leak of 2272 byte(s) in 48 object(s) allocated from:
#0 0x5
On 11/09/2019 19:16, Greg Kurz wrote:
> On Wed, 11 Sep 2019 14:04:51 +1000
> David Gibson wrote:
>
>> From: Alexey Kardashevskiy
>>
>> SLOF implements one itself so let's remove it from QEMU. It is one less
>> image and simpler setup as the RTAS blob never stays in its initial place
>> anyway
Patchew URL: https://patchew.org/QEMU/20190912014442.5757-1-js...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH] docker: add sanitizers back to clang build
Message-id: 20190912014442.5757-1-js...@redhat
On 11/09/2019 18:46, Greg Kurz wrote:
> On Wed, 11 Sep 2019 14:04:50 +1000
> David Gibson wrote:
>
>> From: Alexey Kardashevskiy
>>
>> We are going to use spapr_build_fdt() for the boot time FDT and as an
>> update for SLOF during handling of H_CAS. SLOF will apply all properties
>> from the
Signed-off-by: Wei Yang
---
migration/migration.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index fbdabd34d9..cae3e894ad 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -3023,7 +3023,7 @@ static MigThrError
On Fri, Aug 23, 2019 at 09:07:50AM +0800, Wei Yang wrote:
>On Thu, Aug 22, 2019 at 12:24:32PM +0200, Paolo Bonzini wrote:
>>On 21/03/19 09:25, Wei Yang wrote:
>>> PHYS_MAP_NODE_NIL is assigned to PhysPageEntry.ptr in case this is not a
>>> leaf entry, while map->nodes_nb range in [0, nodes_nb_alloc
Allow machines to configure CNTFRQ via a property if the ARM core
supports the generic timer. This is necessary on e.g. the ASPEED AST2600
SoC where the generic timer clock is run at 800MHz or above. The default
value for CNTFRQ remains at 62.50MHz (based on GTIMER_SCALE).
CNTFRQ is a read-as-writ
Comparing the spice debug logs, where I see this with QEMU 4.0.0 without
the bug:
(remote-viewer:19270): GSpice-DEBUG: 00:05:21.201: channel-display.c:1979
display-2:0: received new monitors config from guest: n: 1/4
(remote-viewer:19270): GSpice-DEBUG: 00:05:21.201: channel-display.c:1997
displ
Finding a minimal case did shed some light on this.
Using QEMU's native graphics window, this works fine:
$ /usr/bin/qemu-system-x86_64 \
-m 1G \
-blockdev
raw,node-name=install_iso,read-only=on,file.driver=file,file.filename=/mnt/losable/ISOs/archlinux-2019.09.01-x86_64.iso
\
-device
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffscrn' and 'mffscrni' instructions.
'mffscrn' and 'mffscrni' are identical to 'mffsl', except they
Sorry, in comment #2 for the native graphics window command line, I
copied from the wrong trial. The argument for QXL should have been
included, because that works with a native graphics window:
(...bootindex=0) \
-vga qxl
--
You received this bug notification because you are a member of
Test the input of basic, time suffixes, float, invaild, trailing and
overflow.
Signed-off-by: Tao Xu
---
No changes in v11.
New patch in v10.
---
tests/test-cutils.c | 199
1 file changed, 199 insertions(+)
diff --git a/tests/test-cutils.c b/tests/
Add optional builtin type time, fallback is uint64. This type use
qemu_strtotime_ps() for pre-converting time suffix to numbers.
Signed-off-by: Tao Xu
---
No changes in v11.
New patch in v10.
---
include/qapi/visitor-impl.h | 4
include/qapi/visitor.h | 9 +
qapi/opts-vis
From: Liu Jingqi
HMAT is defined in ACPI 6.3: 5.2.27 Heterogeneous Memory Attribute Table
(HMAT). The specification references below link:
http://www.uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
It describes the memory attributes, such as memory side cache
attributes and bandw
To convert strings with time suffixes to numbers, support time unit are
"ps" for picosecond, "ns" for nanosecond, "us" for microsecond, "ms"
for millisecond or "s" for second.
Signed-off-by: Tao Xu
---
No changes in v11.
New patch in v10.
---
include/qemu/cutils.h | 1 +
util/cutils.c
From: Liu Jingqi
This structure describes the memory access latency and bandwidth
information from various memory access initiator proximity domains.
The latency and bandwidth numbers represented in this structure
correspond to rated latency and bandwidth for the platform.
The software could use
This series of patches will build Heterogeneous Memory Attribute Table (HMAT)
according to the command line. The ACPI HMAT describes the memory attributes,
such as memory side cache attributes and bandwidth and latency details,
related to the Memory Proximity Domain.
The software is expected to use
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And in 5.2.27.3
Memory Proximity Domain Attributes Structure, the attached initiator is
defined as where the memory controller responsible for a memory proximity
domain
Add tests for time input such as zero, around limit of precision,
signed upper limit, actual upper limit, beyond limits, time suffixes,
and etc.
Signed-off-by: Tao Xu
---
No changes in v11.
New patch in v10.
---
tests/test-keyval.c| 125 +
tests/test
ACPI table HMAT has been introduced, QEMU now builds HMAT tables for
Heterogeneous Memory with boot option '-numa node'.
Add test cases on PC and Q35 machines with 2 numa nodes.
Because HMAT is generated when system enable numa, the
following tables need to be added for this test:
tests/acpi-tes
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Reviewed-by: Daniel Black
Signed-off-by: Liu Jingqi
Signed-off-by: Tao Xu
From: Liu Jingqi
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi
Signed-off-
From: Liu Jingqi
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize the performance
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-18-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINER
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <201906070
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-10-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/bitops.h | 38 +
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signe
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by: Philip
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-22-ys...@users.sourceforge.jp>
Tested-by
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-23-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Yoshinori Sato
---
qapi/machine.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index ca26779f1a..70398c521f 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -28,7 +28,7 @@
'data' : [ 'aarch64', 'alpha', 'ar
From: Philippe Mathieu-Daudé
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 8
1 file changed, 8 insertions(+)
diff --git a/
Hello.
This patch series is added Renesas RX target emulation.
Changes for v23.
Follow master changes.
Changes for v22.
Added some include.
Changes for v21.
rebase latest master.
Remove unneeded hmp_info_tlb.
Chanegs for v20.
Reorderd patches.
Squashed v19 changes.
Changes for v19.
Follow tcg
This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-2-ys...@users
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-3-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted from
From: Philippe Mathieu-Daudé
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-11-ys...@users.sourceforge.jp>
Tested-by: Philippe Math
v21 changes
Add cpu-param.h
Remove CPU_COMMON
rx_load_image move to rx-virt.
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-4-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
Signed-off-by: Richard Hender
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-1
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t arch:rx
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-t
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-6-ys...@users.sourcefo
On Thu, 12 Sep 2019, at 15:52, Cédric Le Goater wrote:
> On 12/09/2019 05:25, Andrew Jeffery wrote:
> > Allow machines to configure CNTFRQ via a property if the ARM core
> > supports the generic timer. This is necessary on e.g. the ASPEED AST2600
> > SoC where the generic timer clock is run at 8
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-8-ys...@users.sourcef
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philip
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
v23 changes.
Add missing includes.
v21 changes.
rx_load_image move to rx-virt.c
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-17-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-D
On 12/09/2019 05:25, Andrew Jeffery wrote:
> Allow machines to configure CNTFRQ via a property if the ARM core
> supports the generic timer. This is necessary on e.g. the ASPEED AST2600
> SoC where the generic timer clock is run at 800MHz or above. The default
> value for CNTFRQ remains at 62.50MHz
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-5-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
include/disas/dis-asm.h |5 +
target/rx/disas.c | 1480 +
Patchew URL: https://patchew.org/QEMU/20190912053638.4858-1-tao3...@intel.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!
Eric Blake writes:
> On 9/11/19 12:21 PM, Eric Blake wrote:
>> On 9/11/19 11:15 AM, Sergio Lopez wrote:
>>> On creation, the export's AioContext is set to the same one as the
>>> BlockBackend, while the AioContext in the client QIOChannel is left
>>> untouched.
>>>
>>> As a result, when using da
Alex Bennée writes:
> Markus Armbruster writes:
[...]
>> Please advise why TCG plugins don't undermine the GPL. Any proposal to
>> add a plugin interface needs to do that.
>
> I'm not sure what we can say about this apart from "ask your lawyer".
I'm not asking for a legal argument, I'm asking
Ping.
Pavel Dovgalyuk
> -Original Message-
> From: dovgaluk [mailto:dovga...@ispras.ru]
> Sent: Monday, August 26, 2019 3:19 PM
> To: Paolo Bonzini; pavel.dovga...@ispras.ru
> Cc: qemu-devel@nongnu.org; Qemu-devel
> Subject: Re: [Qemu-devel] [PULL 15/36] memory: fix race between TCG and
Allow machines to configure CNTFRQ via a property if the ARM core
supports the generic timer. This is necessary on e.g. the ASPEED AST2600
SoC where the generic timer clock is run at 800MHz or above. The default
value for CNTFRQ remains at 62.50MHz (based on GTIMER_SCALE).
CNTFRQ is a read-as-writ
301 - 377 of 377 matches
Mail list logo
