v21 changes
Add cpu-param.h
Remove CPU_COMMON
rx_load_image move to rx-virt.
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-4-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-4-ys...@users.sourceforge.jp>
Signed-off-by: Richard
From: Richard Henderson
We were eliding all zero indexes. It is only ld==0 that does
not have an index in the instruction. This also allows us to
avoid breaking the final print into multiple pieces.
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id:
From: Philippe Mathieu-Daudé
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-11-ys...@users.sourceforge.jp>
Tested-by: Philippe
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-18-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-5-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
---
include/disas/dis-asm.h |5 +
target/rx/disas.c | 1480
On Fri, 2019-09-06 at 14:17 +0100, Daniel P. Berrangé wrote:
> On Mon, Aug 26, 2019 at 04:51:01PM +0300, Maxim Levitsky wrote:
> > Signed-off-by: Maxim Levitsky
> > ---
> > crypto/block-luks.c | 64 +
> > 1 file changed, 41 insertions(+), 23
On Wed, Sep 11, 2019 at 05:51:25PM +0200, Eric Auger wrote:
> Host kernel within [4.18, 5.3] report an erroneous KVM_MAX_VCPUS=512
> for ARM. The actual capability to instantiate more than 256 vcpus
> was fixed in 5.4 with the upgrade of the KVM_IRQ_LINE ABI to support
> vcpu id encoded on 12 bits
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
Patchew URL: https://patchew.org/QEMU/20190912053638.4858-1-tao3...@intel.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
Patchew URL:
https://patchew.org/QEMU/20190912060701.4642-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v24 00/22] Add RX archtecture support
Message-id:
On Fri, 2019-09-06 at 14:11 +0100, Daniel P. Berrangé wrote:
> On Mon, Aug 26, 2019 at 04:50:59PM +0300, Maxim Levitsky wrote:
> > This is just to make qcrypto_block_luks_open more
> > reasonable in size.
> >
> > Signed-off-by: Maxim Levitsky
> > ---
> > crypto/block-luks.c | 254
On Thu 12 Sep 2019 01:33:05 AM CEST, John Snow wrote:
>> This restriction comes from commit 095a9c58ce12afeeb90c2 from 2018.
>
> You accidentally typed a reasonably modern date. It's from *2008*!
Oh my, and I reviewed the message 3 times ... if this one gets committed
please correct the date.
Wei Yang wrote:
> Signed-off-by: Wei Yang
Reviewed-by: Juan Quintela
for(i = 0; i < 0; i++)
printf("Beginning is with double n, not double g");
From: Richard Henderson
There are so many different forms of each RX instruction
that it will be very useful to be able to look at the bytes
to see on which path a bug may lie.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id:
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20190607091116.49044-10-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/bitops.h | 38
From: Richard Henderson
Issue an error if no kernel, no bios, and not qtest'ing.
Fixes make check-qtest-rx: test/qom-test.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-16-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-17-ys...@users.sourceforge.jp>
Signed-off-by: Richard Henderson
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to
From: Richard Henderson
This has consistency with prt_ri(). It loads all data before
beginning output. It uses exactly one call to prt() to emit
the full instruction.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id:
From: Philippe Mathieu-Daudé
Add two tests for the rx-virt machine, based on the recommended test
setup from Yoshinori Sato:
https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03586.html
- U-Boot prompt
- Linux kernel with Sash shell
These are very quick tests:
$ avocado run -t
On Thu, 12 Sep 2019 11:50:53 +1000
Alexey Kardashevskiy wrote:
>
>
> On 11/09/2019 19:16, Greg Kurz wrote:
> > On Wed, 11 Sep 2019 14:04:51 +1000
> > David Gibson wrote:
> >
> >> From: Alexey Kardashevskiy
> >>
> >> SLOF implements one itself so let's remove it from QEMU. It is one less
>
Tried sending you a message @ginf, but haven't heard back from you so I'm
posting here instead;
What kind of debug trace do you want me to give you logs from?
$ /opt/qemu4/bin/qemu-system-x86_64 -d help
Log items (comma separated):
out_asm show generated host assembly code for each
This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-Id:
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-3-ys...@users.sourceforge.jp>
Reviewed-by: Richard Henderson
Message-Id: <20190607091116.49044-3-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
[PMD: Removed tlb_fill, extracted
changes.
Cleanup cpu.c.
simplify rx_cpu_class_by_name and rx_load_image move to rx-virt.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190912
Testing binaries bellow.
u-boot
Download - https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz
starting
From: Philippe Mathieu-Daudé
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-virt.c | 8
1 file changed, 8 insertions(+)
diff --git
Alex Bennée writes:
> Markus Armbruster writes:
[...]
>> Please advise why TCG plugins don't undermine the GPL. Any proposal to
>> add a plugin interface needs to do that.
>
> I'm not sure what we can say about this apart from "ask your lawyer".
I'm not asking for a legal argument, I'm asking
On Wed, Sep 11, 2019 at 05:51:24PM +0200, Eric Auger wrote:
> Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
> allow injection of interrupts along with vcpu ids larger than 255.
> Let's encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
> ABI when needed.
>
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
On Thu, 12 Sep 2019, at 15:52, Cédric Le Goater wrote:
> On 12/09/2019 05:25, Andrew Jeffery wrote:
> > Allow machines to configure CNTFRQ via a property if the ARM core
> > supports the generic timer. This is necessary on e.g. the ASPEED AST2600
> > SoC where the generic timer clock is run at
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato
Reviewed-by: Alex Bennée
Reviewed-by:
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
v23 changes.
Add missing includes.
v21 changes.
rx_load_image move to rx-virt.c
Signed-off-by: Yoshinori Sato
Message-Id: <20190616142836.10614-17-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe
On 12/09/2019 05:25, Andrew Jeffery wrote:
> Allow machines to configure CNTFRQ via a property if the ARM core
> supports the generic timer. This is necessary on e.g. the ASPEED AST2600
> SoC where the generic timer clock is run at 800MHz or above. The default
> value for CNTFRQ remains at
Ping.
Pavel Dovgalyuk
> -Original Message-
> From: dovgaluk [mailto:dovga...@ispras.ru]
> Sent: Monday, August 26, 2019 3:19 PM
> To: Paolo Bonzini; pavel.dovga...@ispras.ru
> Cc: qemu-devel@nongnu.org; Qemu-devel
> Subject: Re: [Qemu-devel] [PULL 15/36] memory: fix race between TCG and
Allow machines to configure CNTFRQ via a property if the ARM core
supports the generic timer. This is necessary on e.g. the ASPEED AST2600
SoC where the generic timer clock is run at 800MHz or above. The default
value for CNTFRQ remains at 62.50MHz (based on GTIMER_SCALE).
CNTFRQ is a
From: Richard Henderson
Note that the ld == 3 case handled by prt_ldmi is decoded as
XCHG_rr and cannot appear here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-21-ys...@users.sourceforge.jp>
Tested-by:
From: Richard Henderson
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-22-ys...@users.sourceforge.jp>
From: Richard Henderson
Collected, to be used in the next patch.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Yoshinori Sato
Signed-off-by: Yoshinori Sato
Message-Id: <20190607091116.49044-23-ys...@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Signed-off-by: Yoshinori Sato
---
qapi/machine.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index ca26779f1a..70398c521f 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -28,7 +28,7 @@
'data' : [ 'aarch64', 'alpha',
Eric Blake writes:
> On 9/11/19 12:21 PM, Eric Blake wrote:
>> On 9/11/19 11:15 AM, Sergio Lopez wrote:
>>> On creation, the export's AioContext is set to the same one as the
>>> BlockBackend, while the AioContext in the client QIOChannel is left
>>> untouched.
>>>
>>> As a result, when using
11.09.2019 20:59, John Snow wrote:
>
>
> On 9/11/19 11:13 AM, Vladimir Sementsov-Ogievskiy wrote:
>> 07.08.2019 19:27, John Snow wrote:
>>>
>>>
>>> On 8/6/19 12:19 PM, Vladimir Sementsov-Ogievskiy wrote:
06.08.2019 19:09, Max Reitz wrote:
> On 06.08.19 17:26, Vladimir
On Wed, 11 Sep 2019 at 14:14, Alex Bennée wrote:
> It does seem a bit weird that userspace linux-user does do semihosting
> whereas EL0 in softmmu doesn't. Is that because we are effectively
> short-circuiting what a real ARM kernel would be doing for EL0?
It's because the "not for EL0" is a
Prior to that patch, the parsed encryption settings
were already stored into the QCryptoBlockLUKS but not
used anywhere but in qcrypto_block_luks_get_info
Using them simplifies the code
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
crypto/block-luks.c | 169
Another minor refactoring
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
crypto/block-luks.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index 9e59a791a6..b759cc8d19 100644
--- a/crypto/block-luks.c
+++
This way we can store the header we loaded, which
will be used in key management code
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
crypto/block-luks.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
crypto/block-luks.c | 63 -
1 file changed, 40 insertions(+), 23 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index c6045da33e..0d155c6614 100644
---
On Wed, Sep 11, 2019 at 08:06:19PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Use the automatic read unlocker in migration/ram.c;
> only for the cases where the unlock is at the end of the function.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
>
a) spice 0.14.2. Also spice-gtk 0.37, and spice-protocol 0.14.0.
b) Swapping with "-device qxl-vga,max_outputs=1" does fix the problem.
Swapping with "-device qxl-vga" still has the bug.
c) Knowing b, would the bisect still help? If needed, sure, I will.
--
You received this bug notification
add PnvHomer device model to emulate homer memory access
for pstate table, occ-sensors, slw, occ static and dynamic
values for Power8 and Power9 chips.
Signed-off-by: Balamuruhan S
---
hw/ppc/Makefile.objs | 1 +
hw/ppc/pnv.c | 30 +
hw/ppc/pnv_homer.c | 272
emulate occ common area region with occ sram device model which
occ and skiboot uses it to communicate regarding sensors, slw
and HWMON in PowerNV emulated host.
Reviewed-by: Cédric Le Goater
Signed-off-by: Balamuruhan S
---
hw/ppc/pnv.c | 8 +
hw/ppc/pnv_occ.c | 78
On Fri, 2019-09-06 at 15:04 +0100, Daniel P. Berrangé wrote:
> On Fri, Aug 30, 2019 at 11:56:03PM +0300, Maxim Levitsky wrote:
> > This implements the encryption key management
> > using the generic code in qcrypto layer
> > (currently only for qemu-img amend)
> >
> > This code adds another
* Peter Xu (pet...@redhat.com) wrote:
> We've got max-postcopy-bandwidth parameter but it's not applied
> correctly after a postcopy recovery so the recovered migration stream
> will still eat the whole net bandwidth. Fix that up.
>
> Reported-by: Xiaohui Li
> Signed-off-by: Peter Xu
Queued
On Thu, 12 Sep 2019 at 11:17, Daniel P. Berrangé wrote:
> I think forcing recompile for each release is reasonable protection
> to make it less atttractive to create license violating closed source
> plugins.
I'm just not sure that a plugin that, for instance, does
"whenever the guest makes a
Bisection is not going well at all with this code base!
Before your last reply, I started, and the first between 4.0.0 and 4.1.0
is aae6500972 which fails compilation:
==
...
CC stubs/pci-host-piix.o
CC stubs/ram-block.o
CC stubs/ramfb.o
CC stubs/fw_cfg.o
Kevin Wolf writes:
> Am 11.09.2019 um 23:33 hat Eric Blake geschrieben:
>> On 9/11/19 12:21 PM, Eric Blake wrote:
>> > On 9/11/19 11:15 AM, Sergio Lopez wrote:
>> >> On creation, the export's AioContext is set to the same one as the
>> >> BlockBackend, while the AioContext in the client
Am 11.09.2019 um 13:00 hat Max Reitz geschrieben:
> On 11.09.19 12:31, Kevin Wolf wrote:
> > Am 11.09.2019 um 12:00 hat Max Reitz geschrieben:
> >> So all in all I think it’s best to make the callback mandatory and add
> >> two global helper functions. That’s simple enough and should prevent
> >>
Peter Maydell writes:
> On Thu, 12 Sep 2019 at 11:42, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > If we fail a semihosting call we should always set the
>> > semihosting errno to something; we were failing to do
>> > this for some of the "check inputs for sanity" cases.
>> >
>>
Peter Maydell writes:
> Factor out the implementation of SYS_WRITE via the
> new function tables.
>
> The #ifdef around the declaration/initialization of the
> local 'env' variable is unfortunate but necessary, because
> the softmmu-semi.h version of lock_user implicitly uses 'env',
> but the
Peter Maydell writes:
> Factor out the implementation of SYS_READ via the
> new function tables.
"As for SYS_WRITE we need env for lock_user in system emulation."?
>
> Signed-off-by: Peter Maydell
Either way:
Reviewed-by: Alex Bennée
> ---
> target/arm/arm-semi.c | 57
Libo Zhou writes:
> Alex Bennée writes:
>
>
>> The gdbstub should allow you do full introspection and adding
>> additional registers is fairly easy, see mips_cpu_gdb_read_register function
>> in target/mips/gdbstub.c.
>
>
>
> Hi Alex and Aleksandar,
>
>
> Now I can connect gdb to qemu
Peter Maydell writes:
> The semihosting code has to build for both user-only and softmmu;
> for user-only it needs access to the TaskState struct that holds
> per-thread information. For softmmu we don't need it.
>
> Currently the softmmu set_swi_errno() takes a CPUARMState *,
> which it
Peter Maydell writes:
> Factor out the implementation of SYS_SEEK via the new function
> tables.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
> ---
> target/arm/arm-semi.c | 32 +++-
> 1 file changed, 23 insertions(+), 9 deletions(-)
>
> diff --git
On Fri, 2019-09-06 at 14:34 +0100, Daniel P. Berrangé wrote:
> On Mon, Aug 26, 2019 at 04:51:03PM +0300, Maxim Levitsky wrote:
> > Check that keyslots don't overlap with the data,
> > and check that keyslots don't overlap with each other.
> > (this is done using naive O(n^2) nested loops,
> > but
Markus Armbruster writes:
> Alex Bennée writes:
>
>> Markus Armbruster writes:
> [...]
>>> Please advise why TCG plugins don't undermine the GPL. Any proposal to
>>> add a plugin interface needs to do that.
>>
>> I'm not sure what we can say about this apart from "ask your lawyer".
>
> I'm
On Thu, 12 Sep 2019 at 09:57, Auger Eric wrote:
>
> Hi Peter,
> On 9/12/19 10:42 AM, Peter Maydell wrote:
> > Is there really no place to put this check in common code?
> Not sure what you mean by common code here? Do you mean in a common code
> for ARM machines (I don't think we have any atm)
* key_bytes -> master_key_len
* payload_offset = payload_offset_sector (to emphasise that this isn't byte
offset)
* key_offset -> key_offset_sector - same as above for luks slots
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
crypto/block-luks.c | 91
This is just to make qcrypto_block_luks_open more
reasonable in size.
Signed-off-by: Maxim Levitsky
---
crypto/block-luks.c | 235
1 file changed, 127 insertions(+), 108 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index
This function will be used later to store
new keys to the luks metadata
Signed-off-by: Maxim Levitsky
---
crypto/block-luks.c | 304 ++--
1 file changed, 181 insertions(+), 123 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index
Check that keyslots don't overlap with the data,
and check that keyslots don't overlap with each other.
(this is done using naive O(n^2) nested loops,
but since there are just 8 keyslots, this doesn't really matter.
Signed-off-by: Maxim Levitsky
---
crypto/block-luks.c | 52
During PowerNV boot skiboot populates the device tree by
retrieving base address of homer/occ common area from
PBA BARs and prd ipoll mask by accessing xscom read/write
accesses.
Reviewed-by: Cédric Le Goater
Signed-off-by: Balamuruhan S
---
hw/ppc/pnv_xscom.c | 34
On Thu, 12 Sep 2019 at 10:03, Alex Bennée wrote:
>
> Well the first thing will be we are not intending to offer a guaranteed
> ABI. While we don't want to be changing it at a whim there shouldn't be
> an expectation that the plugin interface will maintain backwards
> compatibility (unlike the
Hi All,
This is follow-up patch that implements HOMER and OCC SRAM device
models to emulate homer memory and occ common area access for pstate
table, occ sensors, runtime data and slw.
Currently skiboot disables the homer/occ code path with `QUIRK_NO_PBA`,
this quirk have to be removed in
On Wed, Sep 11, 2019 at 08:06:20PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Use the automatic read unlocker in migration/rdma.c.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> migration/rdma.c | 57 ++--
> 1
OK that's interesting - I've got another bug I've been following that's
also fixed by (b).
A bisect would still be interesting; but one place to start might be to try
before and after commit
be812c0
--
You received this bug notification because you are a member of qemu-
devel-ml, which is
Kevin Wolf writes:
> Am 11.09.2019 um 18:15 hat Sergio Lopez geschrieben:
>> On creation, the export's AioContext is set to the same one as the
>> BlockBackend, while the AioContext in the client QIOChannel is left
>> untouched.
>>
>> As a result, when using data-plane,
* Dr. David Alan Gilbert (git) (dgilb...@redhat.com) wrote:
> From: "Dr. David Alan Gilbert"
>
> Commit 78dd48df3 reworked vmxnet3's live migration but left a straggling
> unregister_savevm call. Remove it, although it doesn't seem to have
> any bad effect.
>
> Signed-off-by: Dr. David Alan
* Wei Yang (richard.weiy...@gmail.com) wrote:
> Two cleanup:
>
> Patch #1 make code consistent on calling add_to_iovec
> Patch #2 refine the code to handle the case when buf already flushed
Queued
> v2:
> * wrap common steps into add_buf_to_iovec()
>
> Wei Yang (2):
> migration/qemu-file:
Am 12.09.2019 um 12:13 hat Sergio Lopez geschrieben:
>
> Kevin Wolf writes:
>
> > Am 11.09.2019 um 18:15 hat Sergio Lopez geschrieben:
> >> On creation, the export's AioContext is set to the same one as the
> >> BlockBackend, while the AioContext in the client QIOChannel is left
> >> untouched.
Patchew URL:
https://patchew.org/QEMU/20190912060701.4642-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v24 00/22] Add RX archtecture support
Message-id:
Peter Maydell writes:
> The set_swi_errno() function is called to capture the errno
> from a host system call, so that we can return -1 from the
> semihosting function and later allow the guest to get a more
> specific error code with the SYS_ERRNO function. It comes in
> two versions, one for
Peter Maydell writes:
> Factor out the implementation of SYS_ISTTY via the new function
> tables.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
> ---
> target/arm/arm-semi.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git
On Thu, Sep 05, 2019 at 03:42:03AM -, James Harvey wrote:
> ** Description changed:
>
> Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0.
> Full command line at bottom.
>
> Host gives QEMU two thin LVM volumes. The first is the root filesystem,
> and the second
On Thu, 12 Sep 2019 at 12:44, Alex Bennée wrote:
> Why not pass cs to set_swi_errno and deal with all the differences in
> the helper?
Mmm, that might be better. I think I was going for
not changing the existing use of TaskState in the
code paths that use it.
thanks
-- PMM
Peter Maydell writes:
> SH_EXT_STDOUT_STDERR is a v2.0 semihosting extension: the guest
> can open ":tt" with a file mode requesting append access in
> order to open stderr, in addition to the existing "open for
> read for stdin or write for stdout". Implement this and
> report it via the
On Tue, Sep 10, 2019 at 11:23:50PM +0300, Toe Dev wrote:
> Hey,
> While reviewing I noticed maybe we need to update the spec revision.
> In: nvme_class_init(...)
>
> current code pc->revision=2
> change to: pc->revision=3
> However not really important I think.. Just for consistency.
> When I
Patchew URL:
https://patchew.org/QEMU/20190912060701.4642-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v24 00/22] Add RX archtecture support
Message-id:
* Johannes Berg (johan...@sipsolutions.net) wrote:
> On Wed, 2019-09-11 at 20:15 +0100, Dr. David Alan Gilbert wrote:
>
> > > Extend the protocol slightly, so that a message can be used for kick
> > > and call instead, if VHOST_USER_PROTOCOL_F_IN_BAND_NOTIFICATIONS is
> > > negotiated. This in
On Wed, Sep 11, 2019 at 08:06:18PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> RCU_READ_LOCK_AUTO takes the rcu_read_lock and then uses glib's
> g_auto infrastructure (and thus whatever the compiler's hooks are) to
> release it on all exits of the block.
>
>
There were few trailing comments after `/*` instead in
new line and line more than 80 character, these fixes are
trivial and doesn't change any logic in code.
Reviewed-by: Cédric Le Goater
Signed-off-by: Balamuruhan S
---
hw/ppc/pnv.c | 49 -
1
On Wed, Sep 11, 2019 at 08:06:21PM +0100, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Only in the cases where nothing else interesting happens
> after the unlock.
>
> Signed-off-by: Dr. David Alan Gilbert
> ---
> exec.c | 46
On 12/09/2019 11:30, Balamuruhan S wrote:
> add PnvHomer device model to emulate homer memory access
> for pstate table, occ-sensors, slw, occ static and dynamic
> values for Power8 and Power9 chips.
>
> Signed-off-by: Balamuruhan S
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
>
On Thu, Sep 12, 2019 at 11:54:00AM +0200, Cédric Le Goater wrote:
> On 12/09/2019 11:30, Balamuruhan S wrote:
> > Hi All,
> >
> > This is follow-up patch that implements HOMER and OCC SRAM device
> > models to emulate homer memory and occ common area access for pstate
> > table, occ sensors,
Peter Maydell writes:
> On Thu, 12 Sep 2019 at 11:07, Alex Bennée wrote:
>> Peter Maydell writes:
>> > Wait, what? From my perspective the whole point of the plugin
>> > interface is that it should be stable, in that at least there's
>> > a good chance that a plugin you built will work
Alex Bennée writes:
> The gdbstub should allow you do full introspection and adding
> additional registers is fairly easy, see mips_cpu_gdb_read_register function
> in target/mips/gdbstub.c.
Hi Alex and Aleksandar,
Now I can connect gdb to qemu successfully. And I can use this command to
Patchew URL:
https://patchew.org/QEMU/20190912060701.4642-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v24 00/22] Add RX archtecture support
Message-id:
On Tue, Sep 03, 2019 at 10:25:05PM +0300, Johannes Berg wrote:
> From: Johannes Berg
>
> This is really simple, since we know whether a response is
> already requested or not, so we can just send a (successful)
> response when there isn't one already.
>
> Given that, it's not all _that_ useful
Peter Maydell writes:
> SH_EXT_EXIT_EXTENDED is a v2.0 semihosting extension: it
> indicates that the implementation supports the SYS_EXIT_EXTENDED
> function. This function allows both A64 and A32/T32 guests to
> exit with a specified exit status, unlike the older SYS_EXIT
> function which
On Wed, 11 Sep 2019 at 16:51, Eric Auger wrote:
>
> Host kernel within [4.18, 5.3] report an erroneous KVM_MAX_VCPUS=512
> for ARM. The actual capability to instantiate more than 256 vcpus
> was fixed in 5.4 with the upgrade of the KVM_IRQ_LINE ABI to support
> vcpu id encoded on 12 bits instead
Signed-off-by: Maxim Levitsky
---
crypto/block-luks.c | 158 ++--
1 file changed, 94 insertions(+), 64 deletions(-)
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index ba63e9b442..c3f3488222 100644
--- a/crypto/block-luks.c
+++
On Wed, Jul 31, 2019 at 05:06:39PM +0100, Alex Bennée wrote:
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> [AJB: moved directory and merged various fixes]
> Signed-off-by: Alex Bennée
> +static int plugin_load(struct qemu_plugin_desc *desc)
> +{
> +
* rename the write_func to create_write_func,
and init_func to create_init_func
this is preparation for other write_func that will
be used to update the encryption keys.
No functional changes
Signed-off-by: Maxim Levitsky
Reviewed-by: Daniel P. Berrangé
---
block/crypto.c | 12
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