From: Alistair Francis
Add support for the clock_gettime64/clock_settime64 syscalls.
If your host is 64-bit or is 32-bit with the *_time64 syscall then the
timespec will correctly be a 64-bit time_t. Otherwise the host will
return a 32-bit time_t which will be rounded to 64-bits. This will be
We don't support other 32bit architecture.
Update file to comply with coding style (TAB).
Signed-off-by: Laurent Vivier
Reviewed-by: Taylor Simpson
Message-Id: <20200310103403.3284090-11-laur...@vivier.eu>
Signed-off-by: Laurent Vivier
---
linux-user/s390x/syscall_nr.h | 313
From: Philippe Mathieu-Daudé
freedesktop.org is moving to a GitLab instance,
use the new url.
- https://www.fooishbar.org/blog/gitlab-fdo-introduction/
- https://gitlab.freedesktop.org/freedesktop/freedesktop/-/wikis/home
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
From: Bin Meng
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
From: Rajnesh Kanwal
Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the
From: Alistair Francis
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set
The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request'
into staging (2020-03-16 14:55:59 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv
From: Vladimir Sementsov-Ogievskiy
Firstly, _next_dirty_area is for scenarios when we may contiguously
search for next dirty area inside some limited region, so it is more
comfortable to specify "end" which should not be recalculated on each
iteration.
Secondly, let's add a possibility to limit
From: Vladimir Sementsov-Ogievskiy
Function is internal and even commented as internal. Drop its
definition from .h file.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
Reviewed-by: John Snow
Message-id: 20200205112041.6003-4-vsement...@virtuozzo.com
Signed-off-by: John
From: Vladimir Sementsov-Ogievskiy
We have APIs which returns signed int64_t, to be able to return error.
Therefore we can't handle bitmaps with absolute size larger than
(INT64_MAX+1). Still, keep maximum to be INT64_MAX which is a bit
safer.
Note, that bitmaps are used to represent disk
From: Vladimir Sementsov-Ogievskiy
Use bdrv_dirty_bitmap_next_dirty_area for bitmap_to_extents. Since
bdrv_dirty_bitmap_next_dirty_area is very accurate in its interface,
we'll never exceed requested region with last chunk. So, we don't need
dont_fragment, and bitmap_to_extents() interface
Marc-André Lureau writes:
> Hi
>
> On Sun, Mar 15, 2020 at 4:11 PM Markus Armbruster wrote:
>>
>> This policy suppresses deprecated bits in output, and thus permits
>> "testing the future". Implement it for QMP command results. Example:
>> when QEMU is run with -compat deprecated-output=hide,
On 2020/3/13 下午7:01, Peter Maydell wrote:
On Fri, 14 Feb 2020 at 00:48, Philippe Mathieu-Daudé wrote:
The command is 32-bit, but we are loading the 16 upper bits with
the 'get_uint16(s->scb + 2)' call.
Once shifted by 16, the command bits match the status bits:
- Command
Bit 31 ACK-CX
Patchew URL: https://patchew.org/QEMU/20200316161550.336150-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 00/38] Linux user for 5.0 patches
Message-id: 20200316161550.336150-1-laur...@vivier.eu
Type: series
On 2020/3/17 上午2:14, Peter Xu wrote:
On Mon, Mar 16, 2020 at 01:19:54PM -0400, Michael S. Tsirkin wrote:
On Fri, Mar 13, 2020 at 12:31:22PM -0400, Peter Xu wrote:
On Fri, Mar 13, 2020 at 11:29:59AM -0400, Michael S. Tsirkin wrote:
On Fri, Mar 13, 2020 at 01:44:46PM +0100, Halil Pasic wrote:
On 3/14/20 5:15 AM, Mark Cave-Ayland wrote:
> On 13/03/2020 17:57, John Snow wrote:
>
>> On 3/13/20 4:24 AM, Mark Cave-Ayland wrote:
>>> Following on from the earlier thread "Implement "non 100% native mode"
>>> in via-ide", here is an updated patchset based upon the test cases
>>> sent to me
From: Vladimir Sementsov-Ogievskiy
We are going to introduce bdrv_dirty_bitmap_next_dirty so that same
variable may be used to store its return value and to be its parameter,
so it would int64_t.
Similarly, we are going to refactor hbitmap_next_dirty_area to use
hbitmap_next_dirty together with
Here's a bunch of other patches remaining after the last round,
for some less critical issues. Take these before or after the 5.0
freeze as you like.
Patch 1 is the main thing I think should be considered as a fix:
without it, non-FWNMI guests under KVM see behaviour change with
the FWNMI
Try to be tolerant of errors if the machine check had been recovered
by the host.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_events.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index
Some of the conditions are not as clearly documented as they could be.
Also the non-FWNMI case does not need a large comment.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_events.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr_events.c
The KVM FWNMI capability should be enabled with the "ibm,nmi-register"
rtas call. Although MCEs from KVM will be delivered as architected
interrupts to the guest before "ibm,nmi-register" is called, KVM has
different behaviour depending on whether the guest has enabled FWNMI
(it attempts to do
This enables the mce monitor command for ppc, and adds a spapr
facility to inject machine check exception to a CPU by setting
low level registers.
(qemu) mce 0 0x20 0x80 0xdeadbeef 1
Disabling lock debugging due to kernel taint
MCE: CPU0: machine check (Severe) Host SLB Multihit
Add some messages which explain problems and guest misbehaviour that
may be difficult to diagnose in rare cases of machine checks.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_events.c | 4
hw/ppc/spapr_rtas.c | 4
2 files changed, 8 insertions(+)
diff --git
POWER9 adds scv and rfscv instructions and the system call vectored
interrupt. Linux does not support this instruction yet but it has
been tested with a modified kernel that runs on real hardware.
Signed-off-by: Nicholas Piggin
---
Since v2:
- Rebased on top of FWNMI series
system calls (at least in Linux) use registers r3-r8 for inputs, so
include those registers in the dump.
This also adds a mode for PAPR hcalls, which have a different calling
convention.
Signed-off-by: Nicholas Piggin
---
Since v2:
- Rebased on top of FWNMI series
target/ppc/excp_helper.c |
On 2020/3/17 上午2:01, P J P wrote:
Hello Stefan, Jason,
+-- On Fri, 6 Mar 2020, Stefan Hajnoczi wrote --+
| > +static int
| > +tulip_can_receive(NetClientState *nc)
| > +{
| > +TULIPState *s = qemu_get_nic_opaque(nc);
| > +
| > +if (s->rx_frame_len || tulip_rx_stopped(s)) {
| > +
Patchew URL: https://patchew.org/QEMU/20200316161550.336150-1-laur...@vivier.eu/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 00/38] Linux user for 5.0 patches
Message-id: 20200316161550.336150-1-laur...@vivier.eu
Type: series
On Tue, Mar 17, 2020 at 09:26:15AM +1000, Nicholas Piggin wrote:
> Greg Kurz's on March 17, 2020 4:01 am:
> > On Tue, 17 Mar 2020 00:26:10 +1000
> > Nicholas Piggin wrote:
> >
> >> There should no longer be a reason to prevent TCG providing FWNMI.
> >> System Reset interrupts are generated to
From: Bin Meng
Although the real world SiFive HiFive Unleashed board is a 64-bit
hardware configuration, with QEMU it is possible to test 32-bit
configuration with the same hardware features.
This updates the roms Makefile to add the build rules for creating
the 32-bit OpenSBI firmware image
From: Bin Meng
Upgrade OpenSBI from v0.5 to v0.6 and the pre-built bios images.
The v0.6 release includes the following commits:
dd8ef28 firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils
98f4a20 firmware: Introduce relocation lottery
f728a0b include: Sync-up encoding with
From: Bin Meng
Add two GitLab jobs to build the OpenSBI firmware binaries.
The first job builds a Docker image with the packages requisite
to build OpenSBI, and stores this image in the GitLab registry.
The second job pulls the image from the registry and builds the
OpenSBI firmware binaries.
On 3/16/20 9:41 AM, BALATON Zoltan wrote:
> On Mon, 16 Mar 2020, BALATON Zoltan wrote:
>> On Mon, 16 Mar 2020, Markus Armbruster wrote:
>>> BALATON Zoltan writes:
These are some clean ups to remove more legacy init functions and
lessen dependence on include/hw/ide.h with some
It's easier to work with than a list of tuples, because we can check the
keys for membership.
Signed-off-by: John Snow
---
python/qemu/machine.py| 10 +-
tests/qemu-iotests/040| 12 ++--
tests/qemu-iotests/260| 5 +++--
tests/qemu-iotests/iotests.py | 16
Requires: 20200317004105.27059-1-js...@redhat.com
(This requires the iotests pylint & logging series.)
The basic idea is to make a generic job runtime manager and allow
callers to subclass the manager. Then, instead of adding callback
arguments to the function all the time, we have à la carte
From: Vladimir Sementsov-Ogievskiy
store_bitmap_data() loop does bdrv_set_dirty_iter() on each iteration,
which means that we actually don't need iterator itself and we can use
simpler bitmap API.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
Reviewed-by: John Snow
From: Vladimir Sementsov-Ogievskiy
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Max Reitz
Reviewed-by: John Snow
Message-id: 20200205112041.6003-5-vsement...@virtuozzo.com
Signed-off-by: John Snow
---
include/qemu/hbitmap.h | 21
tests/test-hbitmap.c | 115
From: Vladimir Sementsov-Ogievskiy
We have bdrv_dirty_bitmap_next_zero, let's add corresponding
bdrv_dirty_bitmap_next_dirty, which is more comfortable to use than
bitmap iterators in some cases.
For test modify test_hbitmap_next_zero_check_range to check both
next_zero and next_dirty and add
Eric Blake writes:
> On 3/15/20 9:46 AM, Markus Armbruster wrote:
>> In v4.1.0, we added feature flags just to struct types (commit
>> 6a8c0b5102^..f3ed93d545), to satisfy an immediate need (commit
>> c9d4070991 "file-posix: Add dynamic-auto-read-only QAPI feature"). In
>> v4.2.0, we added them
In the Intel SDM, "Table 18-2. Association of Fixed-Function
Performance Counters with Architectural Performance Events",
we may have a new fixed counter 'TOPDOWN.SLOTS' (since Icelake),
which counts the number of available slots for an unhalted
logical processor. Check commit 6017608936 in the
This series simplifies various memory API calls when creating
memory regions.
Most of the patches are generated with Coccinelle semantic
patches (provided).
Few more cleanups added while writting the patches have been
added.
v1 was 'Let devices own the MemoryRegion they create':
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sh4/shix.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index 68b14ee5e7..f410c08883
The scripts/coccinelle/memory-region-housekeeping.cocci reported:
* TODO
[[view:./hw/arm/stm32f205_soc.c::face=ovl-face1::linb=96::colb=4::cole=26][potential
use of memory_region_init_rom*() in ./hw/arm/stm32f205_soc.c::96]]
* TODO
Avoid orphan memory regions being added in the /unattached QOM
container.
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/g364fb.c | 3 ++-
hw/display/macfb.c | 4 ++--
2 files
Add a semantic patch to remove memory_region_set_readonly() calls
on ROM memory regions.
Signed-off-by: Philippe Mathieu-Daudé
---
.../coccinelle/memory-region-housekeeping.cocci | 15 +++
1 file changed, 15 insertions(+)
diff --git
When a device creates a MemoryRegion without setting its ownership,
the MemoryRegion is added to the machine "/unattached" container in
the QOM tree.
Example with the Samsung SMDKC210 board:
$ arm-softmmu/qemu-system-arm -M smdkc210 -S -monitor stdio
(qemu) info qom-tree
/machine
On 3/16/20 5:00 AM, Philippe Mathieu-Daudé wrote:
> On ARM, the semihosting feature is always required on user-space,
> and is also used by system emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> default-configs/aarch64-linux-user-common.mak | 4
>
Avoid orphan memory regions being added in the /unattached QOM
container.
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/serial.c | 7 ---
1 file changed, 4 insertions(+), 3
The scripts/coccinelle/memory-region-housekeeping.cocci reported:
* TODO
[[view:./hw/ppc/ppc405_boards.c::face=ovl-face1::linb=195::colb=8::cole=30][potential
use of memory_region_init_rom*() in ./hw/ppc/ppc405_boards.c::195]]
* TODO
Since memory region aliases are neither rom nor ram, they are
described as i/o, which is often incorrect. Return instead the
type of the original region we are aliasing.
Signed-off-by: Philippe Mathieu-Daudé
---
memory.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/memory.c b/memory.c
On 3/16/20 6:11 PM, Peter Maydell wrote:
On Mon, 16 Mar 2020 at 16:08, Philippe Mathieu-Daudé wrote:
Xen on ARM does not use QEMU machines [*]. Disable the 'virt'
machine there to avoid odd errors such:
CC i386-softmmu/hw/cpu/a15mpcore.o
hw/cpu/a15mpcore.c:28:10: fatal error:
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Reviewed-by: KONRAD Frederic
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/sparc/leon3.c
On 3/16/20 8:39 AM, Peter Maydell wrote:
> On Fri, 13 Mar 2020 at 16:15, Guenter Roeck wrote:
>>
>> Instantiating apbh_dma and ocotp as unimplemented devices prevents crashes
>> when booting Linux.
>>
>> apbh_dma:
>>
>> [ 14.046518] Unhandled fault: external abort on non-linefetch (0x808) at
Avoid orphan memory regions being added in the /unattached QOM
container.
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/dma/i8257.c | 2 +-
hw/dma/rc4030.c | 4 ++--
2 files changed, 3
On 3/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
> Do not build the virtiofsd helper when configured with
> --disable-system.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: Use single line with ifeq='' (lvivier, rth)
> ---
> Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1
On Mon, 16 Mar 2020 at 18:40, Eduardo Habkost wrote:
>
> On Mon, Mar 16, 2020 at 06:08:54PM +, Peter Maydell wrote:
> > The usual approach is that if you don't have the Linux-specific
> > feature available you quietly fall back to whatever the sensible
> > behaviour is for when the feature
> Le 16/03/2020 à 17:21, Taylor Simpson a écrit :
> >
> >
> >> -Original Message-
> >> From: Laurent Vivier
> >> Sent: Monday, March 16, 2020 3:56 AM
> >> To: qemu-devel@nongnu.org
> >> Cc: Laurent Vivier ; Richard Henderson
> >> ; Riku Voipio ; Taylor
> >> Simpson ; Alistair Francis
>
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ATS instruction will trap.
Not trap, they'll just work.
Otherwise similar comment as for dcpop.
r~
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/arm/helper.c | 20 +++-
> 1 file changed, 11
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the 'Data or unified Cache line Clean by VA to PoP'
> instruction will trap.
>
> Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins")
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/arm/helper.c | 12 ++--
> 1
On 16.03.20 18:57, Cornelia Huck wrote:
> On Mon, 16 Mar 2020 16:04:00 +0100
> Christian Borntraeger wrote:
>
>> On 16.03.20 15:54, Cornelia Huck wrote:
>>> On Mon, 16 Mar 2020 15:47:41 +0100
>>> Janosch Frank wrote:
>>>
On 3/16/20 3:27 PM, Cornelia Huck wrote:
> On Fri, 13 Mar
On Mon, Mar 16, 2020 at 8:15 PM Philippe Mathieu-Daudé
wrote:
>
> This series simplifies various memory API calls when creating
> memory regions.
>
> Most of the patches are generated with Coccinelle semantic
> patches (provided).
> Few more cleanups added while writting the patches have been
>
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static const ARMCPUInfo arm_v4_cpus[] = {
> +{ .name = "ti925t", .initfn = ti925t_initfn },
> +{ .name = "sa1100", .initfn = sa1100_initfn },
> +{ .name = "sa1110", .initfn = sa1110_initfn },
> +{ .name = NULL }
>
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7r_cpu_register_types(void)
> +{
> +const ARMCPUInfo *info = arm_v7r_cpus;
> +
> +while (info->name) {
> +arm_cpu_register(info);
> +info++;
> +}
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by:
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v6_cpu_register_types(void)
> +{
> +const ARMCPUInfo *info = arm_v6_cpus;
> +
> +while (info->name) {
> +arm_cpu_register(info);
> +info++;
> +}
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by:
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> @@ -1,11 +1,5 @@
> # Default configuration for arm-softmmu
>
> -# CONFIG_SEMIHOSTING is always required on this architecture
> -CONFIG_SEMIHOSTING=y
This doesn't belong to this patch. Otherwise,
Reviewed-by: Richard Henderson
r~
On 3/13/20 4:36 AM, Kevin Wolf wrote:
> With a QEMU bug, it can happen that the QEMU process doesn't react to a
> 'quit' QMP command. If we got an exception during previous QMP
> communication (e.g. iotests Timeout expiring), we could also be in an
> inconsistent state where after sending
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v7m_cpu_register_types(void)
> +{
> +const ARMCPUInfo *info = arm_v7m_cpus;
> +
> +while (info->name) {
> +arm_cpu_register(info);
> +info++;
> +}
> +}
Likewise wrt ARRAY_SIZE, otherwise,
Reviewed-by:
On 3/13/20 4:36 AM, Kevin Wolf wrote:
> Waiting for only 1 second proved to be too short on a loaded system,
> resulting in false positives when testing pull requests. Increase the
> timeout a bit to make this less likely.
>
> Signed-off-by: Kevin Wolf
Reviewed-by: John Snow
> ---
>
On Mon, 16 Mar 2020 at 19:36, Richard Henderson
wrote:
> I'm not 100% sure how the system regs function under kvm.
>
> If they are not used at all, then we should avoid them all en masse an not
> piecemeal like this.
>
> If they are used for something, then we should keep them registered and
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Under KVM the ARMv8.1-VHE instruction will trap.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/arm/helper.c | 22 --
> 1 file changed, 12 insertions(+), 10 deletions(-)
What happened to the uses of these
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +++ b/target/arm/kvm32.c
> @@ -22,7 +22,7 @@
> #include "internals.h"
> #include "qemu/log.h"
>
> -static inline void set_feature(uint64_t *features, int feature)
> +static inline void kvm_set_feature(uint64_t *features, int feature)
Why,
Externalisez votre administratif. Gagnez en productivité.
Si vous ne parvenez pas à lire ce message, cliquez ici
Depuis 10 ans, n°1 français de
l'assistance administrative sans embauche
OPTIMISEZ
As we are going to add various semantic changes related to the memory
region API, rename this script to be more generic.
Add a 'usage' header, and an entry in MAINTAINERS to avoid checkpatch
warning.
Signed-off-by: Philippe Mathieu-Daudé
---
...t-ram.cocci => memory-region-housekeeping.cocci} |
Avoid orphan memory regions being added in the /unattached QOM
container.
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/platform-bus.c | 3 ++-
1 file changed, 2 insertions(+), 1
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/cg3.c | 5 ++---
hw/display/tcx.c | 5 ++---
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/display/cg3.c
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_e.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index
On Mon, Mar 16, 2020 at 11:54 AM Philippe Mathieu-Daudé
wrote:
>
> Avoid orphan memory regions being added in the /unattached QOM
> container.
>
> This commit was produced with the Coccinelle script
> scripts/coccinelle/memory-region-housekeeping.cocci.
>
> Signed-off-by: Philippe Mathieu-Daudé
Avoid orphan memory regions being added in the /unattached QOM
container.
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c| 12 ++--
hw/arm/fsl-imx25.c | 10
On Mon, 16 Mar 2020 at 17:43, Laurent Vivier wrote:
>
> The following changes since commit 373c7068dd610e97f0b551b5a6d0a27cd6da4506:
>
> qemu.nsi: Install Sphinx documentation (2020-03-09 16:45:00 +)
>
> are available in the Git repository at:
>
> git://github.com/vivier/qemu.git
This commit was produced with the Coccinelle script
scripts/coccinelle/memory-region-housekeeping.cocci.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c| 1 -
hw/arm/stm32f205_soc.c | 1 -
hw/arm/stm32f405_soc.c | 1 -
3 files changed, 3 deletions(-)
diff --git
Patchew URL: https://patchew.org/QEMU/20200316142928.153431-1-...@irrelevant.dk/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/42] nvme: support NVMe v1.3d, SGLs and multiple namespaces
Message-id:
On Tue, 17 Mar 2020 00:19:05 +0530
Kirti Wankhede wrote:
> On 3/13/2020 11:43 PM, Alex Williamson wrote:
> > On Thu, 12 Mar 2020 23:23:24 +0530
> > Kirti Wankhede wrote:
> >
> > Subject: s/to //
> >
> >> VFIO_IOMMU_DIRTY_PAGES ioctl performs three operations:
> >> - Start pinned and unpinned
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> Semihosting requires TCG. When configured with --disable-tcg, the
> build fails because the 'do_arm_semihosting' is missing. Instead
> of adding more few more #ifdeffery to the helper code, add a stub.
...
> ifeq ($(CONFIG_TCG),y)
>
> -obj-y
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> +static void arm_v5_cpu_register_types(void)
> +{
> +const ARMCPUInfo *info = arm_v5_cpus;
> +
> +while (info->name) {
> +arm_cpu_register(info);
> +info++;
> +}
> +}
Similarly wrt ARRAY_SIZE. Otherwise,
Reviewed-by:
On 3/16/20 12:50 PM, Richard Henderson wrote:
> I much prefer ARRAY_SIZE() to sentinels.
> I know the existing code make much use of them,
> but we don't need to replicate that here.
... but otherwise,
Reviewed-by: Richard Henderson
r~
On 3/13/20 4:36 AM, Kevin Wolf wrote:
> With this, you can send SIGABRT to a hanging test case and you'll get a
> Python stack trace so you know where it was hanging.
>
> Signed-off-by: Kevin Wolf
Reviewed-by: John Snow
Patchew URL: https://patchew.org/QEMU/20200316160634.3386-1-phi...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> When building a KVM-only QEMU, the 'virt' machine is a good
> default :)
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> From: Thomas Huth
>
> Make cpu_register() (renamed to arm_cpu_register()) available
> from internals.h so we can register CPUs also from other files
> in the future.
>
> Signed-off-by: Thomas Huth
> Reviewed-by: Richard Henderson
>
On 3/16/20 9:06 AM, Philippe Mathieu-Daudé wrote:
> ARM_V7M is a concept tied to the architecture. Move it to the
> target/arm/ directory to keep the hardware/architecture separation
> clearer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/Kconfig | 3 ---
> target/Kconfig |
Le 16/03/2020 à 20:27, Taylor Simpson a écrit :
>
>
>> Le 16/03/2020 à 17:21, Taylor Simpson a écrit :
>>>
>>>
-Original Message-
From: Laurent Vivier
Sent: Monday, March 16, 2020 3:56 AM
To: qemu-devel@nongnu.org
Cc: Laurent Vivier ; Richard Henderson
;
linux-user/syscall.c handles the case where TARGET_NR_llseek (one underscore)
is defined and TARGET_NR__llseek (two underscores)
/* Newer kernel ports have llseek() instead of _llseek() */
#if defined(TARGET_NR_llseek) && !defined(TARGET_NR__llseek)
#define TARGET_NR__llseek
From: Felipe Franciosi
Several objects implemented their own uint property getters and setters,
despite them being straightforward (without any checks/validations on
the values themselves) and identical across objects. This makes use of
an enhanced API for object_property_add_uintXX_ptr() which
The mutex and condition variable were never initialized, causing
-mem-prealloc to abort with an assertion failure.
Fixes: 037fb5eb3941c80a2b7c36a843e47207ddb004d4
Reported-by: Marc Hartmayer
Cc: bauerchen
Signed-off-by: Paolo Bonzini
---
util/oslib-posix.c | 7 +++
1 file changed, 7
From: Philippe Mathieu-Daudé
The intel-hda model uses an array of register indexed by the
register address. This array also contains a pair of aliased
registers at offset 0x2000. This creates a huge hole in the
array, which ends up eating 4.6MiB of .rodata (size reported
on x86_64 host, building
From: Christian Ehrhardt
On upgrades the old .so files usually are replaced. But on the other
hand since a qemu process represents a guest instance it is usually kept
around.
That makes late addition of dynamic features e.g. 'hot-attach of a ceph
disk' fail by trying to load a new version of
From: Robert Hoo
And intialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
is faster than its implementation with AVX2 (in my unit test, with
4K buffer, on CascadeLake SP, ~36% faster, buffer_zero_avx512()
Cédric Le Goater's on March 17, 2020 4:15 am:
> On 3/16/20 3:26 PM, Nicholas Piggin wrote:
>> Provide for an alternate delivery location, -1 defaults to the
>> architected address.
>
> I don't know what is the best approach, to override the vector addr
> computed by powerpc_excp() or use a
From: Robert Hoo
And intialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
is faster than its implementation with AVX2 (in my unit test, with
4K buffer, on CascadeLake SP, ~36% faster, buffer_zero_avx512()
From: Julio Faracco
When HAX is enabled (--enable-hax), GCC 9.2.1 reports issues with
snprintf(). Replacing old snprintf() by g_strdup_printf() fixes the
problem with boundary checks of vm_id and vcpu_id and finally the
warnings produced by GCC.
For more details, one example of warning:
CC
From: Philippe Mathieu-Daudé
Install the SASL library to build the VNC SASL auth protocol code.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20200309122454.22551-3-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
501 - 600 of 640 matches
Mail list logo
