From: "Edgar E. Iglesias"
Add DMA memory-region property to externally control what
address-space this DMA operates on.
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git
The current interface includes a loop; change it to load a
single element. We will then be able to use the function
for ld{2,3,4} where individual vector elements are not adjacent.
Replace each call with the simplest possible loop over active
elements.
Reviewed-by: Peter Maydell
Signed-off-by:
Maybe the fastest way to implement hardfloats for ppc could be run them by
default and until some fpu instruction request for FPSCR register.
At this time probably we want to check for some exception.. so QEMU could come
back to last fpu instruction executed and re-execute it in softfloat taking
This new interface will allow targets to probe for a page
and then handle watchpoints themselves. This will be most
useful for vector predicated memory operations, where one
page lookup can be used for many operations, and one test
can avoid many watchpoint checks.
Signed-off-by: Richard
Signed-off-by: Stephen Long
---
Right now, there is no log2 function for half precision floats, so I'm
not sure how to proceed. Currently, I just added a TODO comment.
target/arm/helper-sve.h| 3 +++
target/arm/sve.decode | 4
target/arm/sve_helper.c| 3 +++
30.04.2020 17:27, Kevin Wolf wrote:
The test case forgot to specify the null-co size for the target node.
When adding a check to backup that both sizes match, this would fail
because of the size mismatch and not the behaviour that the test really
wanted to test.
Fixes:
On 4/30/20 1:04 AM, Markus Armbruster wrote:
> John Snow writes:
>
>> On 4/21/20 5:42 AM, Philippe Mathieu-Daudé wrote:
>>> QEMU Python scripts have been moved in commit 8f8fd9edba4 ("Introduce
>>> Python module structure"). Use the same sys.path modification used
>>> in the referenced commit
Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 40 +
target/arm/translate.c | 26 +
target/arm/neon-shared.decode | 5 +
3 files changed, 46
Convert the VCADD (vector) insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 37 +
target/arm/translate.c | 11 +-
target/arm/neon-shared.decode | 3 +++
3 files changed, 41 insertions(+), 10 deletions(-)
Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings. At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.
We follow the same pattern we did for the VFP decodetree conversion
(commit
Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 19 +
We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.
Signed-off-by: Peter Maydell
---
target/arm/translate.h | 17 +
target/arm/translate-a64.c
Convert the VQSHL, VRSHL and VQRSHL insns in the 3-reg-same
group to decodetree. We have already implemented the size==0b11
case of these insns; this commit handles the remaining sizes.
TODO: find out from rth why decodetree insists on VSHL going
into the group...
Signed-off-by: Peter Maydell
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VFM[AS]L (vector) insns to decodetree. This is the last
> insn in the legacy decoder for the 3same_ext group, so we can
> delete the legacy decoder function for the group entirely.
>
> Note that in disas_thumb2_insn() the parts of this
From: Philippe Mathieu-Daudé
When converted to use GByteArray in commits 462474d760c and
a010bdbe719, the call to stfq_p() was removed. This call
serialize a float.
Since we now use a GByteArray, we can not use stfq_p() directly.
Introduce the gdb_get_float64() helper to load a float64 register.
When the gdbstub code was converted to the new API we missed a few
snafus in the various guests. Add a simple gdb test script which can
be used on all our linux-user guests to check for obvious failures.
Signed-off-by: Alex Bennée
---
v2
- use EXTRA_RUNS to queue the tests so as not to break
BALATON Zoltan writes:
> On Tue, 28 Apr 2020, Alex Bennée wrote:
>> 罗勇刚(Yonggang Luo) writes:
>>> I am confusing why only inexact are set then we can use hard-float.
>>
>> The inexact behaviour of the host hardware may be different from the
>> guest architecture we are trying to emulate and
This test seems flaky and reports attachment even when we failed to
negotiate the architecture. However the fetching of the guest
architecture will fail tripping up the gdb AttributeError which will
trigger our early no error status exit from the test
Signed-off-by: Alex Bennée
---
From: "Edgar E. Iglesias"
Add support for stream fragments.
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index 101d32a965..87be9cade7 100644
---
First use of the new helper functions, so we can remove the
unused markup. No longer need a scratch for user-only, as
we completely probe the page set before reading; system mode
still requires a scratch for MMIO.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 182
1 file changed, 111 insertions(+), 71 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 1560129b08..ad7e10f1e7 100644
---
Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
Signed-off-by: Stephen Long
---
I'm not too sure about the casting I'm doing willy nilly in the helper
functions, but I think they should be ok. Also, there might be some avenues
for optimization when translating similar to asr_zpzi and lsl_zpzi.
This patchseries starts in on the job of converting the Arm
Neon decoder to decodetree.
Neon insns come in three major parts:
* the 'v8.0-and-later' extensions
* the 'loads and stores' group
* the 'data processing' group
This patchset converts all of the v8.0-and-later extensions
and the
We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder. Push the feature
Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 14 ++
target/arm/translate.c | 21 ++---
target/arm/neon-dp.decode | 5 +
3 files changed, 21 insertions(+), 19
Convert the Neon "load/store multiple structures" insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 124
target/arm/translate.c | 91 +--
target/arm/neon-ls.decode | 7 ++
3 files
Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
decodetree. These are the last integer operations in the
3-reg-same group.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 44 +
target/arm/translate.c | 24 +-
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Somewhere along theline we accidentally added a duplicate
> "using D16-D31 when they don't exist" check to do_vfm_dp()
> (probably an artifact of a patchseries rebase). Remove it.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-vfp.inc.c
30.04.2020 17:27, Kevin Wolf wrote:
This tests that the backup job catches situations where the target node
has a different size than the source node. It must also forbid resize
operations when the job is already running.
Signed-off-by: Kevin Wolf
Thanks!
Reviewed-by: Vladimir
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load/store multiple structures" insns to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 124
> target/arm/translate.c | 91 +--
>
28.04.2020 17:51, Vladimir Sementsov-Ogievskiy wrote:
28.04.2020 14:08, Max Reitz wrote:
On 28.04.20 10:55, Vladimir Sementsov-Ogievskiy wrote:
Hi!
I wanted to resend my "[PATCH 0/4] fix & merge block_status_above and
is_allocated_above", and returned to all the inconsistencies about
From: "Edgar E. Iglesias"
Auto-clear PHY CR Autoneg bits. This makes this model
work with recent Linux kernels.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_axienet.c
From: "Edgar E. Iglesias"
Add support for fragmented packets from the DMA.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index
From: "Edgar E. Iglesias"
Remove unncessary cast, buf is already uint8_t *.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index
On Wed, 29 Apr 2020 15:59:58 +0200
Gerd Hoffmann wrote:
> The _STA method dates back to the days where we had a static DSDT. The
> device is listed in the DSDT table unconditionally and the _STA method
> checks a bit in the isa bridge pci config space to figure whenever a
> given is isa device
From: "Edgar E. Iglesias"
Stream descriptor by descriptor from memory instead of
buffering entire packets before pushing. This enables
non-packet streaming clients to work and also lifts the
limitation that our internal DMA buffer needs to be able
to hold entire packets.
Signed-off-by: Edgar E.
Since we converted back to cpu_*_data_ra, we do not need to
do this ourselves.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/target/arm/sve_helper.c
For contiguous predicated memory operations, we want to
minimize the number of tlb lookups performed. We have
open-coded this for sve_ld1_r, but for correctness with
MTE we will need this for all of the memory operations.
Create a structure that holds the bounds of active elements,
and metadata
.
Accidental? So maybe what you need is actually something else then -
avoid *removing* the device when it's powered down.
You don’t get it. It is not hypervisor admins who are unplugging it. It is
the end users. Even RedHat customers want this feature. See following
resources:
Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.
Signed-off-by: Peter Maydell
---
target/arm/translate-vfp.inc.c | 6 --
1 file changed, 6 deletions(-)
diff --git
Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 37 +
target/arm/translate.c | 11 +-
target/arm/neon-shared.decode | 11 ++
3 files
Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 22 ++
target/arm/translate.c | 23 +++
target/arm/neon-dp.decode | 8
3 files changed,
Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to
decodetree. These are the only remaining 'pairwise' operations,
so we can delete the pairwise-specific bits of the old decoder's
for-each-element loop now.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 63
Convert the Neon floating point VFMA and VFMS insn to decodetree.
These are the last insns in the 3-reg-same group so we can
remove all the support/loop code from the old decoder.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 41
target/arm/translate.c |
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VCMLA (vector) insns in the 3same extension group to
> decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 37 +
> target/arm/translate.c | 11 +-
>
Now we have support for debugging over a unix socket for linux-user
lets use it in our test harness.
Signed-off-by: Alex Bennée
---
tests/guest-debug/run-test.py | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/tests/guest-debug/run-test.py
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 5bf94d28cf..07f7698155 100644
--- a/include/hw/core/cpu.h
+++
Follow the model set up for contiguous loads. This handles
watchpoints correctly for contiguous stores, recognizing the
exception before any changes to memory.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 285
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 208 +---
1 file changed, 109 insertions(+), 99 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index ad7e10f1e7..f1870aabc2 100644
---
On 30/04/2020 16:20, Markus Armbruster wrote:
>> Ah I see now, these aliases are for individual properties rather than
>> objects. What I
>> was trying to ask was if it were possible to have something like this:
>>
>> /machine (SS-5-machine)
>> /builtin
>> /nic0 -> link to "lance" device
Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 44 +
target/arm/translate.c | 28 +++--
target/arm/neon-dp.decode | 9
Convert the Neon SHA instructions in the 3-reg-same group
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 139
target/arm/translate.c | 46 +--
target/arm/neon-dp.decode | 10 +++
3 files changed, 151
Convert the 64-bit element insns in the 3-reg-same group
to decodetree. This covers VQSHL, VRSHL and VQRSHL where
size==0b11.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 62 +
target/arm/translate.c | 38 ++--
Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to
decodetree. These are 'pairwise' operations.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 71 +
target/arm/translate.c | 16 +---
target/arm/neon-dp.decode | 9
David Hildenbrand writes:
> On 28.04.20 18:34, Markus Armbruster wrote:
>> Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and
>> s390_features[S390_FEAT_PCC_CMAC_EAES_256].name is
>> "pcc-cmac-eaes-256". The former is obviously a pasto.
>>
>> Impact:
>>
>> * s390_feat_bitmap_to_ascii()
Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same
insns to decodetree. (These are all the remaining non-accumulation
instructions in this group.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 60 +
target/arm/translate.c
On 4/30/20 9:28 AM, Stephen Long wrote:
> Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
>
> Signed-off-by: Stephen Long
> ---
>
> I'm not too sure about the casting I'm doing willy nilly in the helper
> functions, but I think they should be ok. Also, there might be some avenues
> for
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load/store single structure to one lane" insns to
> decodetree.
>
> As this is the last set of insns in the neon load/store group,
> we can remove the whole disas_neon_ls_insn() function.
>
> Signed-off-by: Peter Maydell
> ---
>
None of the sve helpers use TCGMemOpIdx any longer, so we can
stop passing it.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 5 -
target/arm/sve_helper.c| 14 +++---
target/arm/translate-sve.c | 17 +++--
3 files
Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 35 +
target/arm/translate.c | 13 +---
target/arm/neon-shared.decode | 3 +++
3 files changed,
Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to
decodetree.
Since VMLA and VMLS accumulate into the destination register, we add
a reads_vd parameter to do_3same_fp() which tells it to load the
old value into vd before calling the callback function, in the same
way that the
Convert the Neon VHADD insns in the 3-reg-same group to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 62 +
target/arm/translate.c | 4 +--
target/arm/neon-dp.decode | 2 ++
3 files changed, 65 insertions(+), 3
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Add the infrastructure for building and invoking a decodetree decoder
> for the AArch32 Neon encodings. At the moment the new decoder covers
> nothing, so we always fall back to the existing hand-written decode.
>
> We follow the same pattern we did
On 29.04.20 10:54, Christian Borntraeger wrote:
>
>
> On 28.04.20 19:13, David Hildenbrand wrote:
>> On 28.04.20 18:34, Markus Armbruster wrote:
>>> Both s390_features[S390_FEAT_PCC_CMAC_AES_256].name and
>>> s390_features[S390_FEAT_PCC_CMAC_EAES_256].name is
>>> "pcc-cmac-eaes-256". The
Hi,
As another release is cut from the tree we start again the collection
of patches fixes and enhancements that weren't yet ready to be
released on an unsuspecting world.
Some of these patches have been seen before in my random collection
series but these are all gdbstub related, This includes
It seems older and non-multiarach aware GDBs might not fail gracefully
when faced with something they don't know. For example when faced with
a target XML for s390x the Ubuntu 18.04 gdb will generate an internal
fault and prompt for a core dump.
Work around this by invoking GDB in a more batch
As gdb will generally be talking to "foreign" guests lets use that if
we can. Otherwise the chances of gdb barfing are considerably higher.
Signed-off-by: Alex Bennée
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index
Signed-off-by: Stephen Long
---
I made the changes Richard requested. I took out the status field for
the helper function.
include/fpu/softfloat.h| 5 +++
target/arm/helper-sve.h| 4 +++
target/arm/sve.decode | 4 +++
target/arm/sve_helper.c| 63
The goal here is to support MTE, but there's some cleanup to do.
Technically, we have sufficient interfaces in cputlb.c now, but it
requires multiple tlb lookups on different interfaces to do so.
Adding probe_access_flags() allows probing the tlb and getting out
some of the flags buried in the
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 223 ++--
1 file changed, 79 insertions(+), 144 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 7992a569b0..9365e32646 100644
---
On 4/30/20 10:20 AM, Stephen Long wrote:
> +DO_ZPZ_FP(flogb_s, float32, H1_4, float32_log2)
> +DO_ZPZ_FP(flogb_d, float64, , float64_log2)
Please read the instruction description more carefully. The result is not the
full log2 of the input:
> This instruction returns the signed integer
Convert the VFM[AS]L (vector) insns to decodetree. This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns
Convert the Neon VQRDMLAH and VQRDMLSH insns in the 3-reg-same group
to decodetree. These don't use do_3same() because they want to
operate on VFP double registers, whose offsets are different from the
neon_reg_offset() calculations do_3same does.
Signed-off-by: Peter Maydell
---
Convert the Neon "load single structure to all lanes" insns to
decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 73 +
target/arm/translate.c | 55 +
target/arm/neon-ls.decode | 5 +++
3 files
On 4/30/20 11:09 AM, Peter Maydell wrote:
> We were accidentally permitting decode of Thumb Neon insns even if
> the CPU didn't have the FEATURE_NEON bit set, because the feature
> check was being done before the call to disas_neon_data_insn() and
> disas_neon_ls_insn() in the Arm decoder but was
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 54 +
target/arm/translate.c | 10 ++
target/arm/neon-dp.decode | 8 +
3 files changed, 65 insertions(+),
Convert the Neon integer 3-reg-same compare insns VCGE, VCGT,
VCEQ, VACGE and VACGT to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 5 +
target/arm/translate.c | 39 ++---
target/arm/neon-dp.decode | 5 +
3
On Thu, 30 Apr 2020 at 11:19, Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29'
> into staging (2020-04-29 15:07:33 +0100)
>
> are
We don't really need to track this fd beyond the initial creation of
the socket. We already know if the system has been initialised by
virtue of the gdbserver_state so lets remove it. This makes the later
re-factoring easier.
Signed-off-by: Alex Bennée
---
v1
- fix coding style issue
---
While debugging over TCP is fairly straightforward now we have test
cases that want to orchestrate via make and currently a parallel build
fails as two processes can't use the same listening port. While system
emulation offers a wide cornucopia of connection methods thanks to the
chardev
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 40 +
> target/arm/translate.c | 26 +
>
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the Neon "load single structure to all lanes" insns to
> decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 73 +
> target/arm/translate.c | 55
We currently have target-endian versions of these operations,
but no easy way to force a specific endianness. This can be
helpful if the target has endian-specific operations, or a mode
that swaps endianness.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
Use the "normal" memory access functions, rather than the
softmmu internal helper functions directly.
Since fb901c905dc3, cpu_mem_index is now a simple extract
from env->hflags and not a large computation. Which means
that it's now more work to pass around this value than it
is to recompute it.
On 4/30/20 5:59 PM, Peter Maydell wrote:
On Tue, 28 Apr 2020 at 18:26, Philippe Mathieu-Daudé wrote:
MIDR_EL1 a 64-bit system register with the top 32-bit being RES0.
This fixes when compiling with -Werror=conversion:
target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
Typo "empty" in patch subject.
On 4/30/20 5:46 PM, Igor Mammedov wrote:
Since 5.0 QEMU uses hostmem backend for allocating main guest RAM.
The backend however calls mbind() which is typically NOP
in case of default policy/absent host-nodes bitmap.
However when runing in container with
On Wed, 29 Apr 2020 16:00:02 +0200
Gerd Hoffmann wrote:
> Add helper function to add fw_cfg device,
> also move code to hw/i386/fw_cfg.c.
>
> Signed-off-by: Gerd Hoffmann
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
> ---
> hw/i386/fw_cfg.h | 1 +
>
Convert the Neon "load/store single structure to one lane" insns to
decodetree.
As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 89 +++
Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be
Convert the V[US]DOT (vector) insns to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 32
target/arm/translate.c | 9 +
target/arm/neon-shared.decode | 4
3 files changed, 37 insertions(+), 8 deletions(-)
Convert the Neon integer VPADD 3-reg-same insns to decodetree. These
are 'pairwise' operations. (Note that VQRDMLAH, which shares the
same primary opcode but has U=1, has already been converted.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 2 ++
target/arm/translate.c
Convert the Neon VRHADD, VHSUB and VABD 3-reg-same insns to
decodetree. (These are all the other insns in 3-reg-same which were
using GEN_NEON_INTEGER_OP() and which are not pairwise or
reversed-operands.)
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 3 +++
Convert the NEON VABA insn in the 3-reg-same group to decodetree.
This is the only insn in this group which does an integer
accumulate into the destination register.
Signed-off-by: Peter Maydell
---
target/arm/translate-neon.inc.c | 76 +
target/arm/translate.c
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
> to decodetree. These are the last ones in the group so we can remove
> all the legacy decode for the group.
>
> Note that in disas_thumb2_insn() the parts of this encoding space
> where
From: KONRAD Frederic
Currently "cf-core.xml" is sent to GDB when using any m68k flavor. Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfire FPU instead of the default m68881 FPU.
This is not OK because the m68881 floats registers are 96 bits wide
On 4/30/20 11:09 AM, Peter Maydell wrote:
> Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
> to decodetree.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate-neon.inc.c | 35 +
> target/arm/translate.c | 13 +---
>
The only caller of cpu_watchpoint_address_matches passes
TARGET_PAGE_SIZE, so the bug is not currently visible.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index
From: "Edgar E. Iglesias"
Since we're missing a maintainer, add myself.
Signed-off-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8cbc1fac2b..9f504e32df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2311,6
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 350c4b451b..d656a1f05c 100644
--- a/include/exec/exec-all.h
+++
Handle all of the watchpoints for active elements all at once,
before we've modified the vector register. This removes the
TLB_WATCHPOINT bit from page[].flags, which means that we can
use the normal fast path via RAM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
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